摘要:

Bit-serial systolic sorting in very large scale integration (VLSI) is considered. Lower bounds on the area, computation time, and flush time for such a sorter are derived for three different input formats, namely the bitwise, the wordwise and the unconstrained formats. The logic design and CMOS circuit design of an optimal bit-serial wordwise systolic sorter are presented. The performance characteristics of the designed chip are discussed.

DOI:10.1049/ip-e.1987.0022

出版商:IEE    

年代:1987

数据来源: IET

摘要:

The VIPER 32-bit microprocessor has been invented at the UK Royal Signals and Radar Establishment (RSRE) for use in highly safetycritical military and civil systems. Throughout, formal mathematical methods have been used to prove that the gate-level realisations conform to a top-level specification. The paper explains the various layers of documentation produced, starting with the use of Michael Gordon's LCF-LSM (based on Meta-Language, ML) at the higher levels, proceeding via the use of John Morison's ELLA hardware description language at lower levels, to multiple VLSI implementations. It is intended to show that this route for designing synchronous VLSI circuits promises a practical means for industry to produce validated designs.

DOI:10.1049/ip-e.1987.0023

出版商:IEE    

年代:1987

数据来源: IET

摘要:

The paper presents a taxonomy for parallel processing systems. Because of technological limitations, high-speed computing has to be achieved nowadays by innovative architectures whose distinctive features cannot be clearly brought out by any of the taxonomies proposed to date. The paper discusses the drawbacks of these taxonomies before proposing a new method of classification based on some dominant architectural features, such as the level of concurrency, method of algorithm realisation, execution characteristic and control structure. The principal aim of proposing a new taxonomy is to develop a nomenclature which can be used to describe the salient features of all the types of parallel processing systems that have been proposed to date. In the last part of the paper it is shown how the nomenclature suggested in the proposed scheme of classification can be used to describe the ‘pure’ high-speed computing systems such as systolic array, pipeline processor, multiprocessor, data-flow processor, multifunction processor, array processor, associative processor and also the systems formed by hybridation of these ‘pure’ systems.

DOI:10.1049/ip-e.1987.0025

出版商:IEE    

年代:1987

数据来源: IET

摘要:

The paper considers the important problem of fast computation of iterative matrix equations. Three architectures for fast implementation of Faddeev's matrix inversion algorithm are described. The recursive nature of Faddeev's algorithm is indicative of many other algorithms, based on the Cayley-Hamilton theorem. All such algorithms seem well suited to the class of orbital architectures reported by Porter and specialised herein. The architectures presented here are essentially 3-dimensional structures. They clearly demonstrate several advantages over comparable 2-dimensional structures particularly with respect to speed and I/O requirements. Besides, the presented architectures are chosen to highlight various 3-dimensional solutions and associated tradeoffs that are representative of the subject class of problems.

DOI:10.1049/ip-e.1987.0027

出版商:IEE    

年代:1987

数据来源: IET

摘要:

Decoder synchronisation for the general class of variable-length T-codes may, with finite probability, be significantly delayed. However, although the T-codes have been shown to be statistically synchronisable with unbounded synchronisation delay, decoder synchronisation occurs generally within fewer than three characters. The paper further presents proof that during delayed synchronisation events, most of the decoded characters will be correct. It is also shown that the total number of incorrect characters received during the decoder synchronisation period is bounded by q + 1, where q is the degree of augmentation for the set in use. This feature of the T-codes may be used to practical advantage for effective error control in systems which are subjected to particularly high error rates.

DOI:10.1049/ip-e.1987.0029

出版商:IEE    

年代:1987

数据来源: IET