摘要:

The functional and VLSI design of a novel one-of-Nbus arbitration circuit for a time-shared bus-interconnected multiprocessor system is presented. The proposed system is a multilevel, hierarchical, two-bit cellular processor structure. The arbitration protocol of rotating priority has been customised to produce a hierarchical, fairness-oriented, rotating-priority protocol that guarantees efficient and deadlock-free time sharing of the bus, with better complexity measures compared to both rotating- and unequal-priority protocols.

DOI:10.1049/ip-e.1993.0041

出版商:IEE    

年代:1993

数据来源: IET

摘要:

Active contour models (snakes) are commonly used for locating the boundary of an object in computer vision applications. The minimisation procedure is the key problem to solve in the technique of active contour models. In this paper, a minimisation method for an active contour model using Hopfield networks is proposed. Due to its network structure, it lends itself admirably to parallel implementation and is potentially faster than conventional methods. In addition, it retains the stability of the snake model and the possibility for inclusion of hard constraints. Experimental results are given to demonstrate the feasibility of the proposed method in applications of industrial pattern recognition and medical image processing.

DOI:10.1049/ip-e.1993.0042

出版商:IEE    

年代:1993

数据来源: IET

摘要:

The paper addresses the problem of testing the check bits in RAMs with on-chip ECC. A solution is proposed in which the check bits are tested in parallel with the testing of the information bits. The solution entails finding a class of parity-check matrices that have the property that all the check bits can be tested for pattern-sensitive faults while the information bits are being tested, without any increase in the length of the test sequence. Further, the parity-check matrices are such that there is no loss in error-correction capabilities, and there is no penalty in the worst-case delay of the error-correcting logic.

DOI:10.1049/ip-e.1993.0043

出版商:IEE    

年代:1993

数据来源: IET

摘要:

A system has been developed to perform multilevel logic synthesis onto PALs for designs that will not fit in two-level sum of products form. The procedure is based upon the application of technology dependent selective collapse algorithms on a multilevel circuit. The multilevel circuit may be obtained using a number of different synthesis strategies. The packages have been implemented in C and added to SIS, the sequential synthesis system developed at Berkeley. Results compare favourably with the best previous system known.

DOI:10.1049/ip-e.1993.0044

出版商:IEE    

年代:1993

数据来源: IET

摘要:

Design diversity has emerged as a powerful mechanism for incorporating software fault tolerance in ultra-reliable systems. In this paper we study the trade-offs available during the development process of fault-tolerant software employing the recovery block approach [2]. When the total available testing time is bounded, our analysis determines how appropriately to allocate testing time to the various redundant modules that make up the fault tolerant system so as to maximise its reliability. This requires a study of the interactions between the various modules in the software system. For example error coverage and the false alarm probability of acceptance test in the recovery block scheme may be interrelated and it may not be possible to simultaneously improve both. Hence there exists a trade-off between acceptance test coverage and false alarm probability. The impact of such trade-offs on system reliability is also studied.

DOI:10.1049/ip-e.1993.0045

出版商:IEE    

年代:1993

数据来源: IET

摘要:

The paper demonstrates the effects of single stuck-at faults in Huffman-model asynchronous sequential logic circuits (ASLCs). The fault effects include equivalent-state redundant faults, invalid-state redundant faults and state oscillations. Equivalent-state redundant faults in ASLCs may be generated by violation of the fundamental mode constraint noncritical races or delays. On the other hand, invalid-state redundant faults are caused either by the existence of invalid states, or by improperly assigning the ‘don't-care’ terms. State oscillations are generally caused by the presence of critical races. Based on the fault effects, this paper presents a set of rules for synthe-sising oscillation-free ASLCs in the presence of faults. As far as synthesising testable ASLCs is concerned, the race-free UDC state assignment is much better than STT state assignment.

DOI:10.1049/ip-e.1993.0046

出版商:IEE    

年代:1993

数据来源: IET

摘要:

With recent advances in vertical-integration technology, it is now reasonable to consider a three-dimensional IC structure containing either partially or completely stacked active layers. Thus it is possible to have stacked terminals at the channel edges. In this case, each terminal is constrained to a specific layer and therefore may only enter the channel on the layer to which it is constrained. For a channel of length λ usingnlayers for routing, it is now possible to have 2nλ terminals on the edges of the channel. A new channel-routing algorithm is presented for routing channels consisting of stacked and constrained terminals. The algorithm employs greedy heuristics, routing the channel column by column from left to right. The router guarantees a solution, although one or more extra columns off the end of the channel may be required. The heuristics of the router can be easily modified to rearrange priorities or to add new requirements or constraints. The algorithm has been tested extensively using randomly-generated channel descriptions. Very good solutions were obtained in a short amount of CPU time.

DOI:10.1049/ip-e.1993.0047

出版商:IEE    

年代:1993

数据来源: IET

摘要:

In the paper we make a comparative study of two techniques to design error-detectable array architectures. These techniques are the redundant binary representation (RBR) where the data is encoded in the 1-out-of-3 code; and the two-rail logic where the data is encoded in the 1-out-of-2 code. In recent work, the RBR has been used to achieve online error detection and localisation by checking the data on the array borders. Here we show that another approach is also possible, with less hardware cost, where the checking takes place on the local (processor) level. This provides immediate error detection without delay. The performance of the RBR approaches has been compared with the two-rail approach. The results show that the RBR approaches require more hardware overheads, for small word lengths (n). However, the hardware cost of the two techniques are approximately the same for largen, while the RBR approaches offer much faster arithmetics for alln.

DOI:10.1049/ip-e.1993.0048

出版商:IEE    

年代:1993

数据来源: IET

摘要:

Two-level logic is most often implemented as an inclusive-OR sum of product terms, e.g. with PLAs. Using exclusive-OR (EXOR) sums may simplify the representation and manipulation of Boolean functions and result in more easily testable implementations requiring fewer product terms. However, due to the lack of relevant algorithms and efficient implementation structures, it has not been possible to translate these theoretical advantages into practical benefits. In this paper solutions for the two main problems associated with the use of EXOR sums are presented. On the one hand we describe a new method to minimise functions using two-level EXOR sums of products, on the other hand we present an implementation structure called the XPLA to map the minimisation results to efficient circuit layouts. We show, for a set of benchmark examples, that the minimisation algorithm results in representations with considerably smaller product term counts than previous EXOR minimisation algorithms or sum-of-product minimisation algorithms. We also show, although the EXOR operator is more expensive to implement in today's technologies, that XPLA implementations can be considerably more compact than PLAs in some cases, and give increased testability.

DOI:10.1049/ip-e.1993.0049

出版商:IEE    

年代:1993

数据来源: IET

摘要:

A synthesis algorithm tor Reed-Muller directed acyclic graph (DAG) networks is presented. Based on the circuit cost matrix, the algorithm grows the DAG network from inputs to output, and thus allows the formulation of more accurate criteria for variable selection. By using this algorithm, the quasiminimum DAG network can be found with (n+2)(n−1)/2 variable assignments.

DOI:10.1049/ip-e.1993.0050

出版商:IEE    

年代:1993

数据来源: IET