摘要:

The paper describes the dilemma of the merchant semiconductor company, where increased complexity of semiconductor devices results in increased development costs, while, in many cases, increased complexity means increased specialisation and therefore reduced volumes. The solution proposed is to transfer design to the equipment companies. This solution is only practical if the expertise of the chip designer is embodied in sophisticated computer aids. In this case, the merchant semiconductor company reduces to a silicon foundry. The paper goes on to discuss the two principal techniques available to achieve the above objective, namely gate arrays and the more recently introduced standard cell design methodology. Also discussed is the extension of the standard cell from relatively simple cells to larger parametric cells created to specification using silicon compilers. Some of the more detailed topics briefly discussed include stick diagrams as an alternative methodology, two-layer metal to aid autorouting, the importance of good logic simulation, trend curves for the next 10 years and prediction of some of the problems and some of the products which may result from increased scale of integration.

DOI:10.1049/ip-e.1985.0007

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The design of a gate array chip and process suitable for carrying out integrated circuit design exercises at an undergraduate level is described. The array uses simplicity in both processes and design in order to make these exercises economically feasible. The educational value in the exercise is in introducing the students to process design rules and their interpretation. Also it will teach, in a practical manner, the advantages and disadvantages of a gate array implementation for a given logic system. Integrated injection logic is chosen as the technology because of its simplicity and its inherent suitability for realising gate arrays. The novel features of this process are described. The chip architecture is also described in relation to the constraints on in-house design and processing. It is designed as a multiproject chip, where each project has available ten edge-triggered D-types, 54 three output gate and 20 user pads. A typical design example is given together with the projected timescales for the exercise.

DOI:10.1049/ip-e.1985.0008

出版商:IEE    

年代:1985

数据来源: IET

摘要:

Uncommitted logic arrays have been available to system designers for several years, but have hitherto mainly found application in digital signal processing. In the paper a proprietary communication IC application is described using an ECL array containing a mixture of analogue and digital circuitry. The array regenerates the data signals of a high-speed optical-fibre transmission system.

DOI:10.1049/ip-e.1985.0009

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The circuit design, process and layout techniques used to implement a high-performance silicon integrated circuit for a 565 Mbit/s multiplex and optical-fibre transmission system will be described. The IC contains 6000 transistors and operates at speeds well in excess of those normally achieved using semicustom circuit techniques, while retaining the normal advantages of semicustom design methods.

DOI:10.1049/ip-e.1985.0010

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The structure of programmable logic devices of the PLA type is described and the various device architectures currently available are reviewed. Following a discussion of their evolution, the design techniques necessary for their effective application are presented. Recent developments in computer-aided design and device testing specifically for programmable logic are surveyed. Finally, some comparisons are made with other forms of semicustom circuit.

DOI:10.1049/ip-e.1985.0011

出版商:IEE    

年代:1985

数据来源: IET

摘要:

An historical review of how technological advances leading up to the VLSI technology have changed the computer industry is presented. Two major problems of designing, using VLSI, are then discussed, with a description of how these are being tackled by one computer manufacturer for designing with VLSI in future systems.

DOI:10.1049/ip-e.1985.0012

出版商:IEE    

年代:1985

数据来源: IET

摘要:

Megacell is a complete design package for the creation of complex VLSI chips. It allows system engineers to develop their own custom integrated circuits. The challenge of Megacell was to create a design system that would exploit fully the low-power and high-speed performance of a UK developed 2 μm CMOS technology, while producing the silicon utilisation efficiency typical of full custom design. This was accomplished without losing the now familiar semicustom design attributes of ‘first-time success’, coupled with facilities for the user to complete his own design. The full features of the Megacell design system are described, and projections are made of how its capabilities will be extended as CMOS technology edges towards 1 μm. The provision of a series of cell structures of increasing complexity within Megacell allows the user to optimise his layout, without inducing the uncharacterised variations that would be usual in a full custom design. The cell structure has within it three major types: microcells which are the low-level logic cells found in most array or cell design systems; paracells which are cells of high functional capability, compiled by user software specifically for the customer's application. The paracell is created from parameters, input by the user, as he designs his circuit; and supracells which have the highest complexity and are cells that replicate the function of today's LSI standard products. They include not only digital functions, such as microprocessors, but also analogue blocks such as A/D and D/A convertors. The heart of the Megacell design system is its CAD. Alongside the cell structures, a comprehensive set of integrated design tools has been developed to cover the complete spectrum of user requirements. Included in the system are schematic capture, simulation, test validation and generation, as well as full layout capabilities.

DOI:10.1049/ip-e.1985.0013

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The novel CMOS digital/analogue convertor is intended for use in cell-based semicustom designs. High speed and low power consumption have been achieved using a standard VLSI process without postprocess trimming.

DOI:10.1049/ip-e.1985.0014

出版商:IEE    

年代:1985

数据来源: IET

摘要:

A software system for structured schematic documentation and switch-level simulation of digital integrated circuits is presented. By means of an interactive command language, the user can specify the schematic diagrams which document the actual digital design directly onto a graphical screen. This documentation can be performed hierarchically, in a manner where selected subcircuits are represented by macro symbols instead of all the relevant schematic primitives. This ensures a clear overview of even very complex designs. In addition to this schematic editor, the software system contains a translator which is able to convert the schematic documentation into an electrical specification of the actual design. This specification is the basis for an event-driven switch-level simulation algorithm which is able to calculate very rapidly the behaviour of the actual circuit and to submit warnings when critical races or hazard phenomena are detected. Experiments show that digital circuits, consisting of many thousand digital gates, can be specified and analysed on a mainframe computer during an interactive man-machine dialogue which normally requires a few hours of manual effort and a few minutes of CPU time.

DOI:10.1049/ip-e.1985.0015

出版商:IEE    

年代:1985

数据来源: IET

摘要:

Chip designs should be produced by building from a large selection of appropriate component designs. Each component should be modular, but the resulting design should permit consistency checking. STRICT attempts to embody these principles in a formal notation for the design of integrated circuits.

DOI:10.1049/ip-e.1985.0016

出版商:IEE    

年代:1985

数据来源: IET