摘要:

This paper presents a noveln-way parallel merge module (PMM) that consists of many parallel merge elements (PME) built into the tree structure, to enhance the throughput of hardware merger. The proposed parallel merge module can be used as a passive high speed module to match the data processing rate of other parallel hardware module, such as parallel sorter and data filters, in the backend computers or database machines.

DOI:10.1049/ip-e.1989.0022

出版商:IEE    

年代:1989

数据来源: IET

摘要:

Two new algorithms that facilitate the implementation of RSA in software are described. Both algorithms are essentially concerned with performing modular arithmetic operations on very large numbers, which could be of potential use to applications other than RSA. One algorithm performs modular reduction and the other performs modular multiplication. Both algorithms are based on the use of look-up tables to enable the arithmetic computations to be done on a byte by byte basis.

DOI:10.1049/ip-e.1989.0023

出版商:IEE    

年代:1989

数据来源: IET

摘要:

A very efficient but little known logic design procedure is the search tree algorithm proposed by Thelen [1] for the generation of all prime implicants of a Boolean function. Besides the generation of prime implicants Thelen's algorithm can be used to solve various logic design problems, such as the computation of maximum compatibles, determination of a minimal cover and the computation of prime factors for multilevel logic synthesis [2, 3]. In the paper we present Thelen's algorithm and its application to the problems which arise in the logic design of two-level multiple-output switching circuits. We show that the logic minimisation procedures, such as the expansion of implicants, detection of essential primes, computation of a minimal cover and reduction of prime implicants can be reduced to one problem and efficiently solved by the use of Thelen's algorithm. Based on these new procedures we present two heuristic minimisation algorithms, an iterative Espresso-like minimiser and a very fast one-pass minimiser, and discuss their results. Both minimiser differ from known algorithms [4, 5, 6, 20] in that minimisation is based on only one fundamental (easily programmable) procedure and minimisation of incompletely specified Boolean functions is performed without use of the don't care set. Because of the latter aspect our design algorithms are especially suited for the minimisation of logic functions whosedon't careset is large and/or not explicitly given. The algorithms have been successfully tested in the design of finite state machines and are part of the CAD-system CARLOS [7], a logic synthesis system for the design of multilevel CMOS switching circuits.

DOI:10.1049/ip-e.1989.0024

出版商:IEE    

年代:1989

数据来源: IET

摘要:

In order to provide an arbitrary and fully dynamic connectivity in a network of processors, transport mechanisms must be implemented, which provide the propagation of data from processor to processor, based on addresses contained within a packet of data. Such data transport mechanisms must satisfy a number of requirements, namely deadlock and livelock freedom, good hot-spot performance, high throughput and low latency. The paper proposes a solution to these problems, which allows deadlock free, adaptive, high throughput packet routing to be implemented on networks of processors. Examples are given which illustrate the technique for two-dimensional (2D) array and toroidal networks. The implementation of this scheme on arrays of transputers is considered. The scheme also serves as a basis for very-low latency routing strategy introduced here as well.

DOI:10.1049/ip-e.1989.0025

出版商:IEE    

年代:1989

数据来源: IET

摘要:

A yield model is developed to estimate yield values for the serial superchip. The superchip is a large silicon chip containing many processing elements together with a communication network. Owing to its large area, the superchip concept will not be economically viable if current silicon processing technology and conventional non-redundant VLSI design techniques are employed to implement it. This paper demonstrates the result of yield improvement by employing hardware redundancy. Cost-effectiveness is also measured by the optimality of the employed redundancies.

DOI:10.1049/ip-e.1989.0026

出版商:IEE    

年代:1989

数据来源: IET

摘要:

There are several important issues that must be considered in the design of highly parallel SIMD machines. Factors such as machine programmability, support for flexible interprocessor communications and a suitable I/O system all contribute to the design of a successful SIMD computer system. The microprocessor array (μPA) is an SIMD design study performed in conclusion to an Alvey funded project to design and implement a reconfigurable processor array (RPA), a single-bit processor array design. The design study differs significantly from its predecessor and rectifies its deficiencies, in both technological and programmability areas. The proposal is for an array of 1024, 8-bit wide processing elements, each one of which has its own communications coprocessor. It supports a versatile packet switching network which operates concurrently with processing. Other features include support for high speed floating point operations, fast I/O and novel mechanism to support local conditional statements within the array, which greatly aids programmability.

DOI:10.1049/ip-e.1989.0027

出版商:IEE    

年代:1989

数据来源: IET

摘要:

New algorithms for preconditioning and inversion of symmetric positive-definite matrices are proposed in this paper. These algorithms have a parallel structure and are suitable for realisation on systolic arrays. The algorithms are based on the repeated use of a polynomial preconditioning technique. Matrix-matrix multiplications constitute the major computations in these algorithms. On a systolic array, the total time for either preconditioning or inversion of an (N×N) matrix is of the order ofN. The implementational details of the algorithm on systolic arrays are outlined. Preliminary theoretical analysis on the convergence rate of the algorithms for a specific input parameter combination is presented along with the results of numerical experiments on several matrices.

DOI:10.1049/ip-e.1989.0028

出版商:IEE    

年代:1989

数据来源: IET

摘要:

A number of systolic architectures have appeared over the past few years for performing the discrete Fourier transform (DFT) and fast Fourier transform (FFT) algorithms, using both linear and orthogonal processing networks. The paper shows how a rectangular array ofNCORDIC (co-ordinate digital computer) processing elements can be used to carry out an efficient two-dimensional systolic implementation of theN-point DFT, offering highly attractive throughput rates in relation to otherN-processor solutions, such as the conventional linear systolic array.

DOI:10.1049/ip-e.1989.0029

出版商:IEE    

年代:1989

数据来源: IET

摘要:

Two radiation-hard technologies, E/D-MESFET GaAs and SOS-CMOS Si are compared, from the point of view of propagation delay and VLSI layout area, for different types of adders. The major intention was to evaluate the impact of two technologies on the adder design. However, the overall results are more general. They show how the adder design trade-offs change when the dependency of gate delays on fan-in and fan-out changes. The major conclusion of this research is that traditionally slow adders, like ripple-carry or similar, although still slower than traditionally fast adders, like carry-lookahead or similar, may be better suited for incorporation into GaAs microprocessors with word lengths of up to 32 bits. This is because the delay gap between the two adder groups has decreased and the VLSI area gap between the same two adder groups has increased. Consequently, if simpler adder is incorporated, the remaining area could be ‘invested’ into resources that would speed up the execution of compiled HLL code more than the incorporation of a faster (but area-consuming) adder and a faster system clock.

DOI:10.1049/ip-e.1989.0030

出版商:IEE    

年代:1989

数据来源: IET