摘要:

The history of integrated circuit development has been one of continually decreasing feature size, accompanied by a much more gradual increase in chip dimensions. There are obvious limits to both of these trends. In the case of chip size, clearly, the limit is the whole wafer, offering a circuit area on a 15 cm wafer that is roughly 175 times larger than current VLSI chips. Such a step function in chip size offers a massive increase in potential functional complexity, but also implies a radical rethink of philosophy in design, fabrication, test and packaging. This article discusses the problems associated with the development of WSI technology and reviews some of the strategies that have been adopted in the pursuit of WSI sub-systems.

DOI:10.1049/ip-e.1988.0038

出版商:IEE    

年代:1988

数据来源: IET

摘要:

Since the early 1960s, semiconductor chips have matured from single transistor devices to 1 million transistors per chip. This increase in integration has been achieved by reducing transistor dimensions, and by increasing chip sizes. However, physical limits are being reached as submicrometre dimensions are approached. Therefore, there is need for larger chip, and wafer, sizes. Manufacturers use defect tolerance to maintain the increase in chip complexity; acceptable yields are achieved with larger chip sizes. In the paper, various aspects of defect-tolerant design are investigated. It is suggested that yield improvement is only one of the many possible gains offered by defect tolerence. The advantages and disadvantages of the many approaches to defect tolerance are discussed. Wafer-scale integration appears to be the target size for defect tolerant IC chips, but as wafer size continues to increase, the constraints due to wafer-scale implementation of an architecture must be weighed up against the advantages that such devices offer. The paper also examines a particular subsystem implemented in VLSI, ULSI and WSI, and considers the relative merits of each implementation.

DOI:10.1049/ip-e.1988.0039

出版商:IEE    

年代:1988

数据来源: IET

摘要:

Following the considerable success that linear predictive coding (LPC) has had in speech compression, the technique has been applied to the coding of two-dimensional (2-D) signals such as natural images. Unlike its one-dimensional (1-D) counterpart, the 2-D technique is not guaranteed to be stable. It is found that too much correlation in the signal causes a significant proportion of the analysis frames to produce unstable prediction filters, rendering the decoded image unintelligible. The paper introduces two methods for systematically reducing the signal correlation, and hence improving the so called ‘stability rate’ of a 2-D LPC system. The first method is based on the 2-D Fourier transform, and the second is based on the 2-D Hadamard transform. The effectiveness of each method is illustrated followed by a cost analysis based on algorithm complexity and bit-rate overhead.

DOI:10.1049/ip-e.1988.0040

出版商:IEE    

年代:1988

数据来源: IET

摘要:

The paper presents an algorithm based on scale-space analysis, for the recognition of blurred planar objects. Apart from satisfying the usual requirements for invariance under translation, rotation and scaling, the algorithm is also invariant under blurring, that is, across all levels of detail or scales. The technique makes use of the spatial coincidence of the infiexion points on the object contour at all scales, and of the fact that no new such points are created as the object becomes more blurred. The algorithm therefore searches for the best match of these points at a single scale in the scale-space image. The algorithm was implemented on an IBM/AT in Modula-2 programming language, and was tested out on a group of 20 geographical maps of different sizes and at varying distances from the camera. A recognition rate of 95 to 100% and an average recognition time of 2.5 seconds were obtained by an efficient organisation of the template dictionary.

DOI:10.1049/ip-e.1988.0041

出版商:IEE    

年代:1988

数据来源: IET

摘要:

A procedure for describing an ECL circuit at the gate level is proposed. All voltages and currents which switch during circuit operation are described by logic variables, and thus the ‘stuck line’ model can be effectively applied to describe circuit failures. Faults resulting from open connections and short circuits between transistor terminals are considered in detail.

DOI:10.1049/ip-e.1988.0042

出版商:IEE    

年代:1988

数据来源: IET

摘要:

It is well known that the Euclidean algorithm or its equivalent, continued fractions, can be used to find the error locator polynomial and the error evaluator polynomial in Berlekamp's key equation that is needed to decode a Reed-Solomon (RS) code. In the paper, a simplified procedure is developed and proved to correct erasures as well as errors by replacing the initial condition of the Euclidean algorithm by the erasure locator polynomial and the Forney syndrome polynomial. By this means, the errata locator polynomial and the errata evaluator polynomial can be obtained simultaneously and simply, by the Euclidean algorithm only. With this improved technique, the complexity of time-domain Reed-Solomon decoders for correcting both errors and erasures is reduced substantially from previous approaches. As a consequence, decoders for correcting both errors and erasures of RS codes can be made more modular, regular, simple, and naturally suitable for both VLSI and software implementation. An example illustrating this modified decoding procedure is given for a (15, 9) RS code.

DOI:10.1049/ip-e.1988.0043

出版商:IEE    

年代:1988

数据来源: IET

摘要:

The paper is devoted to designing nonlinear Boolean functions. The first part reviews the case of Boolean functions ofnvariables. The second part addresses the problem of the generation of Boolean permutations to obtain the collection of nonlinear Boolean functions.

DOI:10.1049/ip-e.1988.0044

出版商:IEE    

年代:1988

数据来源: IET

摘要:

Operations in finite fields find diverse applications. Circuits have been designed for carrying out such operations. In the paper, two circuits that carry out multiplication inGF(2p) have been presented. These circuits are suitable for implementation using VLSI techniques, and are simpler than existing circuits. The architecture used here is that of systolic arrays and consists of regular interconnection of simple cells.

DOI:10.1049/ip-e.1988.0045

出版商:IEE    

年代:1988

数据来源: IET