摘要:

In the paper we propose a bipartite, distance-regular topology for interconnection networks to build large multiprocessor systems. The network consists of 2(2m+1[2]) nodes, with diameter 2m+1 and degreem+1. The connectivity for these networks is the best possible and their average internodal distance is roughly equal to half the diameter. These features show that the proposed networks have relatively high densities, and are capable of maximal fault-tolerance. The topology allows efficient self-routing for both the non-faulty and faulty network. For these networks we propose a semi-distributed fault-diagnosis algorithm which requires a relatively small computation overhead and generates considerably lower network traffic. The self-diagnostic scheme is in turn shown to be fault-tolerant. The most remarkable property of this topology is its symmetric partitioning capability, which is based on a combinatorial configuration known as the Hadamard matrix. On the basis of this partitioning property, we propose another semidistributed self-diagnosis algorithm which considerably improves the diagnosability of the partitioned network over the non-partitioned network

DOI:10.1049/ip-e.1990.0021

出版商:IEE    

年代:1990

数据来源: IET

摘要:

The process of detecting edges in an image includes the convolution of the image with an operator or template, whose coefficients are determined by the algorithm in use. By approximating these coefficients to the nearest power-of-two, the convolution operation is greatly speeded-up, since each multiplication can instead be performed by a shift operation. This is attractive both for a software as well as a hardware implementation, since the arithmetic shift operation can be implemented at a lower cost than multiplication. Methods for deriving an integer valued operator and a powers-of-two operator are discussed, and the results obtained with each operator are compared.

DOI:10.1049/ip-e.1990.0022

出版商:IEE    

年代:1990

数据来源: IET

摘要:

The paper discusses a novel systolic implementation of the row-column method for solving the prime factor discrete Fourier transform (DFT) algorithm. It deals, in particular, with the two-factor decomposition where the transform lengthNis an odd multiple of 4. By processing the four-point row-DFTs coefficient by coefficient, rather than DFT by DFT, as is conventionally done, it is seen how pipelined implementations of the row-DFT and column-DFT processes can be performed simultaneously, without need for matrix transposition of the row-DFT output, resulting in a fully pipelined concurrent solution. Hardware efficiency and simplicity is achieved via the computationally attractive Cordic (co-ordinate digital computer) arithmetic, withO(N) throughput requiring (asymptotically) one-quarter of the hardware requirements of establishedN-processor solutions.

DOI:10.1049/ip-e.1990.0023

出版商:IEE    

年代:1990

数据来源: IET

摘要:

In the paper a proposal of a flexible error-correcting codec for data transmission is presented. The field of possible applications is explained. The flexible codec allows implementation of RS and binary BCH codes with variable parameters within the same device. In the future the progress in VLSI technology will permit integration as a flexible one chip channel codec.

DOI:10.1049/ip-e.1990.0024

出版商:IEE    

年代:1990

数据来源: IET

摘要:

A simplified procedure, called the shift-search method, is developed to decode the three possible errors in a (23,12,7) Golay codeword. The algebraic decoding algorithm developed recently by Elia is compared with this algorithm. A computer simulation shows that both algorithms are modular, regular and naturally suitable for either VLSI or software implementation. Both of these algorithms decode efficiently the 1/2-rate (24,12) Golay code for correcting three errors and detecting four errors. The algebraic technique is a slightly faster algorithm in software than the shift-search procedure.

DOI:10.1049/ip-e.1990.0025

出版商:IEE    

年代:1990

数据来源: IET

摘要:

The paper describes the design and philosophy of a mask verification language (MVL) and its compiler. Mask verification tools have to be programmable, because of the large software investment they require, and the speed at which fabrication technology changes. The language described here allows a designer to specify the topological structure of a device (the device description), and to attach to it a procedure to be executed when that device is recognised (the device procedure). The device procedure allows certain geometric qualifications to be placed on the structure. (The device description and procedure, taken together, form a device declaration.) In general, an MVL program will contain several device declarations: one for each realisable type of device of a technology. The description part of a declaration is asynchronous, and the procedural part, which is internally sequential, is executed once for each instance of the device description located on the mask set. Careful choice of the primitives provided allows extensive optimisation of the leaf operations involved, which is extremely important, given the usual size of the mask data-sets.

DOI:10.1049/ip-e.1990.0026

出版商:IEE    

年代:1990

数据来源: IET

摘要:

A systematic design methodology for redundant systolic arrays is proposed. Redundancies consisting of space-shift, time-shift and space-time-shift schemes are applied successfully to detect or mask permanent faults, transient faults or both. Various redundancy designs for different utilisation efficiencies of processor elements can be obtained at the design stage by a dependent graph and its associated algebraic transformation. A customised optimal redundant systolic array design can be achieved for various performance requirements, including throughput rate, latency, average computation time, hardware cost and capabilities of fault detection and fault masking.

DOI:10.1049/ip-e.1990.0027

出版商:IEE    

年代:1990

数据来源: IET