摘要:

N-tuple nets are conceptually a highly parallel architecture. However, high-speed serial emulations ofN-tuple nets offer considerable advantages of flexibility and cost efficiency in applications requiring only moderate bandwidth. In the paper a software technique for designing dynamically evolvedN-tuple nets is described and the process whereby the designed structure can be progressively mapped into hardware to a level determined by the application requirements is illustrated.

DOI:10.1049/ip-e.1987.0045

出版商:IEE    

年代:1987

数据来源: IET

摘要:

We describe a technique to double the throughput of bit-serial computational networks, while retaining the many advantages associated with this architectural approach. In essence this technique relies on a 2-wire radix-4 representation of serial data: a step towards bit parallelism. As the cost of data storage associated with bit-serial architectures is not increased by this technique, it has a favourable effect on overall area-time product. Novel use of the well-known modified-Booth recoding multiplication algorithm results in further area savings. A set of functional building blocks and interfacing conventions is outlined, forming the basis of a cell library for use in a silicon compilation environment.

DOI:10.1049/ip-e.1987.0046

出版商:IEE    

年代:1987

数据来源: IET

摘要:

The paper discusses the design of easily testable counters for use in frequency division circuits. The proposed approach, based on linear feedback shift registers, requires the minimum number of memory elements. The algorithms for counter synthesis and test-pattern generation are described in detail

DOI:10.1049/ip-e.1987.0047

出版商:IEE    

年代:1987

数据来源: IET

摘要:

Several broad classes of nonplanar arrays/architectures are analysed. Included in this are architectures which have a natural interpretation in terms of data flow on the surface of a torus, sphere, cylinder and other geometric forms. A definitive quantification is given of the several architectural classes and architectural reconfiguration is demonstrated to facilitate iterative computations.

DOI:10.1049/ip-e.1987.0048

出版商:IEE    

年代:1987

数据来源: IET

摘要:

The operation and performance of a multiple-processor system with shared buses is analysed. The model developed is applicable to real-time computations consisting of two pipelined tasks in which the first task is partitioned into a number of independent subtasks on separate processors. These processors transmit their output data to the processor(s) executing the second task over shared buses. When the system has a single shared bus, it is shown that its operation becomes periodic after a number of task executions. Expressions for the cycle time and the system throughput are derived. Two schemes are then proposed for scheduling the data transmissions on a multiple-bus system so as to minimise the corresponding cycle times. The computational complexity of the scheduling problems is studied, and exact, approximate and heuristic algorithms are developed for their solution.

DOI:10.1049/ip-e.1987.0049

出版商:IEE    

年代:1987

数据来源: IET

摘要:

The spanning multiaccess channel hypercube (SMCH) is a distributed computer interconnection structure, based on a hypercube topology, where processors are connected using multiaccess channels spanning all dimensional axes. The channel access arbitration is achieved through demand assignment multiple access (DAMA) protocols. We compare the SMCH to the generalised hypercube (GHC), the nearest neighbour mesh hypercube (NNMH), cube connected cycles (CCC), and the Boolean cube (BCube). The comparison shows the SMCH to have excellent performance characteristics, at a cost significantly lower than comparable structures. This is achieved by combining the recent advances in processor interconnection architectures, the economies of scale available with highcapacity channels, and demand assignment multiple-access protocols, to form a highly efficient, cost effective, distributed computer system.

DOI:10.1049/ip-e.1987.0050

出版商:IEE    

年代:1987

数据来源: IET