摘要:

Built-in self-test (BIST) is emerging as an important option for testing VLSI application-specific integrated circuits (ASICs). The advantages of BIST are reviewed in relation to the particular test requirements imposed by ASICs. A suite of programs will be described that facilitate the incorporation of BIST into ASIC designs. The programs comprise a high-level planning tool, operating from functional descriptions of the circuit. A set of programs will also be described that enable the evaluation of the fault coverage achieved when circuits are tested using pseudorandom patterns, and also aid the placement of additional test hardware to improve the level of fault coverage.

DOI:10.1049/ip-e.1988.0025

出版商:IEE    

年代:1988

数据来源: IET

摘要:

Reos is a document image processing system which stores images of paper documents as a bit map on optical discs. These images are displayed on a CRT at a lower resolution compared to the stored data. The conversion and display of the stored information must be performed quickly to achieve an acceptable system response time; since even highly optimised software could not process more than a few thousand pixels per second, a hardware solution capable of processing many millions of pixels per second was developed. The mesh offset algorithm which combines image resampling with convolution, was selected for its performance and ease of mapping onto silicon. The hardware of this algorithm option is suitable for more general purpose image processing tasks such as filtering to reduce noise, or contrast enhancement. A high level description of the system has been mapped onto silicon using a number of design options to provide the best balance between speed of design, performance and die area. The resolution converter in 2.5 μm CMOS double layer metal technology supports scan path test and signature analysis for production test purposes.

DOI:10.1049/ip-e.1988.0026

出版商:IEE    

年代:1988

数据来源: IET

摘要:

Parallelism has found its way into programmable processors as well as dedicated engines such as FFT and digital filters. However, choices of machine architecture are still open. We have evaluated two contrasting types to test their versatility and to compare their performance on algorithms related to military applications. Fine-grain SIMD, and coarse-grain MIMD machines (Mil-DAP and Transputer arrays) have been applied to a spectrum of problems including FFT, two-dimensional operators, associative processing, linear assignment, sorting, dynamic programming and ray tracing. These relate to military needs in spectrum analysis and image correlation, feature extraction from images, ESM, tracking with netted radars, speech recognition and terrain intervisibility. Possibilities for parallelism in combat simulators are also being examined. Each type of processor has been proved versatile and much more powerful than conventional sequential machines. DAP has the advantage on regular low precision algorithms, and on assignment and sorting operations where scatter, gather and shift operations are important. Transputer arrays will (when the T800 version is available) offer a better capability for floating point arithmetic and less regular tasks. The chief conclusion is that both architectures are extremely versatile and VLSIcompatible, and that choices between them will more often hinge on the cost of a minimal system, the quality of the development software and the portability of code, rather than on the fundamental properties of the machine topology.

DOI:10.1049/ip-e.1988.0027

出版商:IEE    

年代:1988

数据来源: IET

摘要:

A systolic array for triangularisation of dense matrices, using Gaussian elimination with partial pivoting, is presented. The adopted algorithm is a slightly modified version of the traditional partial-pivoting algorithm. The modification is aimed at eliminating the need for global communications, without jeopardising the numerical stability of the algorithm. The array triangularises ann×ndense matrix inO(n2) time without any need for costly inter-iteration I/O. The processing elements (PEs) are very simple and all data communications are strictly local. It is shown that an extended array (with n extra PEs) can solve a dense system of equations inO(n2) time. It is also shown that the same array can be modified to implement a scaled column-pivoting strategy.

DOI:10.1049/ip-e.1988.0028

出版商:IEE    

年代:1988

数据来源: IET

摘要:

Sequential versions of those optimisation algorithms which are based on random search heuristics are often too slow to be of value to the interactive user of a CAD workstation. A significant gain in speed can be achieved by using concurrent algorithms to drive an optimising accelerator attached to the workstation. The paper discusses the design and performance of a hardware accelerator which incorporates INMOS transputers. Concurrent versions of two algorithms are described, one relevant to combinatorial optimisation and the other to global optimisation. The mapping of these algorithms on to the transputer hardware is discussed. The application and performance of each algorithm is illustrated by means of a representative problem from the field of electronic engineering.

DOI:10.1049/ip-e.1988.0029

出版商:IEE    

年代:1988

数据来源: IET

摘要:

An approximate Markov model is developed to analyse a clustered multiprocessor interconnection system for processor memory communication. In the proposed network, processors and memories are grouped into clusters utilising locality of communication. Within any cluster processors communicate with the memories through a small crossbar; a synchronous TDM bus interconnects the different clusters. The performance of this organisation has been evaluated by simulating Markov model. This performance evaluation shows that when the probability of request generation between clusters is low the proposed network is comparable to the fully connected crossbar in throughput, while being less complex in hardware requirements. Design considerations for the network are discussed with a view to its VLSI implementation.

DOI:10.1049/ip-e.1988.0030

出版商:IEE    

年代:1988

数据来源: IET

摘要:

The paper presents an integrated procedure, called MCS, for the automated synthesis of microprogrammed controllers in digital systems at the register-transfer (RT) level. To MCS there are two major inputs: a description of the data path of the digital system and a behavioural description of the digital system at the RT level. The result given by MCS is a cost effective controller which can drive the operations of the data path. MCS works in seven major steps: (a) Defining an initial basic controller model; (b) generating sequences of control signals; (c) manipulating control-flow statements; (d) compacting parallel operations; (e) determining the lower bound of control word width; (f) determining the control word format; (g) encoding the control memory. The algorithms that MCS uses in carrying out these steps are described. The paper also describes two experiments in which the MCS is used to synthesise the controllers of two small hypothetical CPUs.

DOI:10.1049/ip-e.1988.0031

出版商:IEE    

年代:1988

数据来源: IET