摘要:

The problem of natural texture segmentation is considered. The technique is based on four texture features derived using the fractal geometry of images. These four features are fractal dimension (FD) of the original image, FD of above average (high) gray level image, FD of below (low) gray level image, and multifractal of order two. A modified box-counting approach is proposed to estimate the FD and computed features all are normalised in the same range [0, 1]. A feature domain smoothing is activated to reduce the spurious segmentation. Next, a nonsupervised clustering approach is used to segment a scene into the desired number of classes. Some supervised techniques like minimum distance classifier andk-nearest neighbour classifier are also considered. Mosaics of various natural textures are generated and the segmentation results are presented to show the efficiency of the technique.

DOI:10.1049/ip-e.1993.0034

出版商:IEE    

年代:1993

数据来源: IET

摘要:

Linear congruential recurrence relations modulo 2eare a very obvious way of producing pseudorandom integer sequences on digital signal processors. The maximum value possible for the period of such a sequence generated by annth-order relation is (2n−l)2e−1. Such a relation can be specified by annth-degree feedback polynomialf(x) withe-bit coefficients. Necessary conditions for the period to be maximal are that at least one of the initialising values should be odd and thatf(x) (mod 2) should be a primitiventh-degree polynomial. These conditions are not sufficient, and there is an extra condition needed onf(x) (mod 4). This condition is here expressed in a form simple enough to verify that large classes of polynomials will give the maximum period. For example (subject tof(x) (mod 2) being primitive)f(x) can be any pentanomial with odd coefficients and degreen>5, or any trinomial with odd coefficients and odd degreen. Other large classes of suitable polynomials are described. In many cases we may determine by inspection whetherf(x) will give the maximal period. These results make it simple, for example, to set up quite distinct recurrence relations to act as independent pseudorandom number generators.

DOI:10.1049/ip-e.1993.0035

出版商:IEE    

年代:1993

数据来源: IET

摘要:

An algorithmic fault tolerant scheme in presented for the solution via LU decomposition of a linear system of equations in the presence of up to two transient hardware faults. In the general case, where the faults affect arbitrary entries in the coefficient matrix array, the methods are based on an application of the extended Euclidean algorithm scheme for decoding BCH and RS codes. In the special case, where the faults are assumed not to affect (distinct) entries in the same row of the array, a simplified algorithm is given with a corresponding reduction in the hardware overhead. After detection, location and correction of the fault-induced errors, the Sherman—Morrison—Woodbury formula is used to determine the correct solution vector of the linear system, without requiring a valid triangular decomposition of the coefficient matrix.

DOI:10.1049/ip-e.1993.0036

出版商:IEE    

年代:1993

数据来源: IET

摘要:

The group of classical graph-theoretic problems, including graph colouring, clique cover, and maximal clique, may be viewed as instances of a general node partitioning problem (NPP). A wide variety of real life problems can be modelled as instances of NPP. Finding an optimal partition for the NPP is said to be NP-complete. In this work a stochastic search by a genetic algorithm (GA) is employed to find a near optimal solution for the NPP. The critical aspects of the GA for NPP, such as the solution representation by elegant data structure, together with genetic operations and selection policies employed in the GA procedure, are also presented. The proposed GA does not require the number of disjunct node sets to be givena priori. Three application problems is VLSI design are solved as instances of NPP. The experimental results presented in each case of these application problems bring out the efficacy of genetic algorithms.

DOI:10.1049/ip-e.1993.0037

出版商:IEE    

年代:1993

数据来源: IET

摘要:

The main advantage of delay-insensitive design of circuits is that it ensures that circuits function correctly independently of delays in their components and wires. Timing constraints do not have to be considered, which facilitates top-down design. Process algebras provide a suitable formalism for specification, design and verification of concurrent systems, but there are few methods for practical compilation of electronic circuits using these algebras. The paper illustrates such a method for the compilation of algebraic expressions to delay-insensitive circuits. Compilation if facilitated by the use of two new forms of the decision wait element. The implementation of these elements is also examined.

DOI:10.1049/ip-e.1993.0038

出版商:IEE    

年代:1993

数据来源: IET

摘要:

A novel model for specifying a delay-insensitive circuit is introduced, in which transition signals and two-phase communication convention are used. In this model, a circuit is described by various states. At each state, an input to the circuit not only produces an output, but also causes a corresponding state transition. Based on this model, a systematic method for synthesising purely delay-insensitive circuits is presented, which is suitable for the design of control, data transmission and data-processing circuits.

DOI:10.1049/ip-e.1993.0039

出版商:IEE    

年代:1993

数据来源: IET

摘要:

The paper describes the implementation of a bit-serial systolic array architecture for a multilayer perceptron. It is shown that both the recall phase and learning phase can be mapped onto a similar systolic array structure, with minor differences. As a result, a combined systolic array structure is proposed for both the recall phase and the learning phase. The design is simulated using the FIRST silicon compiler to solve the exclusive OR problem, and then compared with a 32-bit floating-point simulation. The central element, multiply-and-accumulate operator was fabricated using a 1.2 μm double metal CMOSp-well process by ORBIT semiconductor, and found to perform satisfactorily. The required chips were implemented with the same technology, and performance parameters estimated. Furthermore, the performance of this architecture in solving the NETtalk problem is compared with other implementations.

DOI:10.1049/ip-e.1993.0040

出版商:IEE    

年代:1993

数据来源: IET