1. |
Past, present and future of the computer field |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 4,
1984,
Page 106-112
M.V.Wilkes,
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摘要:
The paper surveys some of the landmarks that have been passed as the computer field has developed from its early inception and comments on some of the issues that are now claiming attention. The paper is based on a lecture given by Prof. Wilkes to the IEE on 16th February 1984.
DOI:10.1049/ip-e.1984.0020
出版商:IEE
年代:1984
数据来源: IET
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2. |
An algorithm for the partitioning of logic circuits |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 4,
1984,
Page 113-118
M.W.Roberts,
P.K.Lala,
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摘要:
The exhaustive testing of today's digital circuits is not possible, owing to the vast test sequences which would have to be applied. Breaking down the circuit into manageable subcircuits (partitioning) makes exhaustive testing practicable. Partitioning has previously been done by the designer of the circuit in rather anad hocmanner. The paper describes an algorithm which can be used to find the partitioning points in a circuit. The algorithm is illustrated for circuits containing reconvergent and nonreconvergent fan-outs.
DOI:10.1049/ip-e.1984.0021
出版商:IEE
年代:1984
数据来源: IET
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3. |
A review of synchronisation and matching in fault-tolerant systems |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 4,
1984,
Page 119-124
W.R.Moore,
N.A.Haynes,
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摘要:
The paper reviews the reasons for and the problems of synchronising the processors of a faulttolerant system and of matching the data in them. It is known that exact solutions require at least (3t+ 1) channels fort-fault-tolerance, but that more economical solutions with only (2t+ 1) channels are feasible when assumptions are made which ensure consistent data in the fault-free processors. The assumptions and the efficiencies of previous algorithms are discussed in the light of overall reliability targets, and the relevance of ‘malicious’ faults and interactive consistency are highlighted. New minimum-hardware solutions are introduced which are particularly suited to microprocessor applications.
DOI:10.1049/ip-e.1984.0022
出版商:IEE
年代:1984
数据来源: IET
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4. |
Programmable variable-rate up/down counter for generating binary logarithms |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 4,
1984,
Page 125-131
H.Y.Lo,
J.H.Lu,
Y.Aoki,
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摘要:
The design of an algorithm for a programmable variable-rate counter for generating precise binary logarithmic functions is presented. The error in log2(l + x), as defined by Iog2(l + x) − x, may be considered as a set of straight lines whose slopes, either positive or negative, are chosen to be integral multiples of a binary fraction. By using a programmable counter whose rate is proportional to the slope of the line segments, the error is corrected. The circuitry is simple because no add operation is needed. The precision of the answer depends upon the number of bits used. In addition, an algorithm to synthesise the variable-rate up/down counter (VRU/DC), thus reducing the number of calculations, is given. It pinpoints the break points for this design, and also specifies the range covered by the segment for optimal precision. The algorithm can also be used to generate the antilogarithm.
DOI:10.1049/ip-e.1984.0023
出版商:IEE
年代:1984
数据来源: IET
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5. |
Electronic control of small hydroelectric schemes using a microcomputer |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 4,
1984,
Page 132-136
S.Kormilo,
P.Robinson,
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摘要:
The role of electronic load controllers in reducing the cost of small hydro schemes is explained with particular reference to the situation in Papua New Guinea. A prototype controller based on an AIM 65 microcomputer is described. Program algorithm and input/output circuitry are covered in detail. Conditions necessary for stable load controller operation are discussed and quantified. Laboratory and field test results are given, with indications of likely future developments.
DOI:10.1049/ip-e.1984.0024
出版商:IEE
年代:1984
数据来源: IET
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6. |
Method of storing route guidance information using quadtrees |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 4,
1984,
Page 137-142
N.B.Taylor,
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摘要:
An electronic route guidance system employing roadside processors will benefit from the provision of a compact method of storing directional information, especially when a large network is involved. This may be particularly relevant where roadside units are periodically downloaded from a central installation. A form of quadtree, the partition tree, offers very efficient data storage together with the ability to support alternative directions for different vehicle types, time periods and other parameters with the minimum use of additional memory. In a network of 40000 nodes, the largest considered, the estimated average size of partition tree is 686 bytes, and the maximum size around 2k bytes. In a main-road-only network, containing 10000 nodes, these figures are approximately halved.
DOI:10.1049/ip-e.1984.0025
出版商:IEE
年代:1984
数据来源: IET
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7. |
Digital line segment coding: A new efficient contour coding scheme |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 4,
1984,
Page 143-147
B.B.Chaudhuri,
M.K.Kundu,
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摘要:
A new coding scheme is proposed for two-tone image contours. The basic idea is to detect digital line segments on the contour and code them using fixed- or variable-length codewords; the present work deals mainly with fixed-length codewords. It is demonstrated that the conventional contour run length coding by Freeman's chain code is a special case of this scheme. The data compressibility of the scheme is studied and the test results on several contours are presented. The results show that the present scheme is superior to the conventional scheme.
DOI:10.1049/ip-e.1984.0026
出版商:IEE
年代:1984
数据来源: IET
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8. |
Time-memory tradeoff in exponentiating a fixed element ofGF(qn)requiring a short reference to the memory |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 4,
1984,
Page 148-150
B.Arazi,
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摘要:
Raising αxto the yth power overGF(qn)can be performed by calculating αymodulo the minimum polynomial of αxand then multiplying the result by an n × n matrix overGF(q). The elements of the matrix are only a function of x and of the generating polynomial of the field. This principle offers a time-memory trade-off when exponentiating a fixed element ofGF(qn), where the multiplications (not the squarings) involved in the standard squareand- multiply process are traded for a reference to a stored n × n matrix. The operations which make use of the stored data consume time which is equivalent to a single multiplication operation over the field, and are performed continuously, where the timeconsuming part of the exponentiation process is performed independently of the stored data. It is then shown how the presented principle enables an efficient implementation overGF(qn)of some variations of Diffie-Hellman public-key distribution system.
DOI:10.1049/ip-e.1984.0027
出版商:IEE
年代:1984
数据来源: IET
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9. |
Digital encoding by means of new T-codes to provide improved data synchronisation and message integrity |
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IEE Proceedings E (Computers and Digital Techniques),
Volume 131,
Issue 4,
1984,
Page 151-153
M.R.Titchener,
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摘要:
A new class of variable-length synchronisable codes offers improved data integrity in the presence of additive and timing errors. Character synchronisation occurs automatically during normal decoding procedures. The estimated improvements obtainable using these codes in the transmission of ASCII text over a noisy channel are shown in a comparison with conventional serial code systems.
DOI:10.1049/ip-e.1984.0028
出版商:IEE
年代:1984
数据来源: IET
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