ISSN:0098-9886    

DOI:10.1002/cta.4490200302

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1992

数据来源: WILEY

摘要:

AbstractNew algorithms for the allocation, assignment and scheduling of a hierarchical data control flow graph (DCFG) with imposed timing constraints are presented. the hierarchical allocation environment performs a probabilistic search through the design space and converges towards a final solution by iteratively calling and interchanging resource utilisation information with the assignment and scheduling subroutines.The allocation, assignment and scheduling problem is posed in a such a way that the specific costs of all hardware elements are taken into account and simultaneously addressed. the proposed algorithms have novel constructive and rejectionless iterative improvement probabilistic components.The effectiveness of the algorithms is demonstrated with the aid of extensive experimental results. In addition to the standard benchmarks, we have studied a broad class of test examples of a very diverse nature, thus covering the global design space. We also discuss how min‐bound estimations are used to more easily and realistically assess the quality of the allocation, assignment and scheduling algorithm

ISSN:0098-9886    

DOI:10.1002/cta.4490200303

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1992

数据来源: WILEY

摘要:

AbstractThe management of foreground memory is a main issue in data path synthesis. the storage of values in registers and register files not only determines the number of each of them but also has a major impact on the interconnect structure. Both the amount of multiplexing and interconnect are crucial factors to both the delay and area of a circuit. In this paper it is shown that when values are grouped into register files before being assigned to actual registers, significant savings (20 per cent) can be obtained in the number of local interconnections and the amount of global interconnect at the expense of only slightly more register area. These results can be enhanced by splitting the read and write phases of registers and even more by introducing serial (re)write operations for the same value. the value grouping is based on edge‐colouring algorithms that provide a sharp upper bound on the number of register groups needed.After value grouping, the registers are allocated for each register file separately. Algorithms for register allocation published up till now have only considered loop‐free data flow graphs. When these algorithms are applied to data flow graphs with loops, unnecessary register transfer operations can be introduced. In this paper a new algorithm is presented that performs a minimal register allocation eliminating all superfluous register transfer operations. Experiments on a benchmark set have shown that in all cases all register transfers could be eliminated at no increase in register cost.This paper provides a deeper insight to the computational complexity of some problems in the area of data path synthesis. It shows that the various subtasks can be solved exactly using polynomial time algorit

ISSN:0098-9886    

DOI:10.1002/cta.4490200304

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1992

数据来源: WILEY

摘要:

AbstractNew methodologies for the ‘design‐oriented’ symbolic analysis of analogue circuits are presented. the objective of this analysis is to obtain results that will give more insight into the circuit behaviour. the feature of the presented methods is to allow the network function to be stated in several parts, with an eventual hierarchical dependence on each other, but without loss of interpretability.Several methods are combined. the first one consists of a rule‐based algorithm for network reduction which allows significant simplification before the main analysis is performed. Initially, simple models can be used, since the effects of parasitic elements can be computed afterwards at little CPU expense, thanks to the implementation of the extra element theorem.3the network is divided into blocks by a simple decomposition algorithm. Each block is analysed and the network function is next calculated.To reduce the size of the calculated expressions, the symbolic calculator uses the concept of ‘correction factor’, based on a comparison between the orders of magnitude of the symbolic terms. A PROLOG prototype tool has been written in order to validate these methods. A simple two‐stage amplifier is taken as an example. the solution contains 11 products, to be compared with the 174 that would give a direct topolog

ISSN:0098-9886    

DOI:10.1002/cta.4490200305

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1992

数据来源: WILEY

摘要:

AbstractTo exploit the increased circuit density available in current technologies for continuous‐time (c‐t) systems, it is proposed to extend the range of analogue design automation to the larger c‐t subsystems, specifically filters, commonly found in communications, mass storage devices and other interfaces to real‐world signals. the synthesis is based onLCladder simulation using only transconductances and grounded capacitors (TGC). the method retains many of the characteristics of digital design automation and therefore allows a direct mapping of these techniques. the TGC approach is shown to require a minimum of component types which are ideally suited to integration in MOS, bipolar or GaAs technologies. A simple example for the automation of c‐t filter designs as well as results of CMOS c‐t filters are included to demonstrate the viability of this approach. Related and equally important areas addressed are tuning, compensation for parasitics

ISSN:0098-9886    

DOI:10.1002/cta.4490200306

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1992

数据来源: WILEY

摘要:

AbstractThis paper describes the router developed for ALPS, the analogue layout prototyping system. the ALPS router employs some classic techniques and contributes a new, fast implementation of a maze‐running algorithm and a new algorithm for finding two disjoint paths in a graph (the so‐called ‘two path problem’). Discussion of these points is coupled with a review of existing routing algorithms and techniques, and comparisons where p

ISSN:0098-9886    

DOI:10.1002/cta.4490200307

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1992

数据来源: WILEY

摘要:

AbstractA new approach to constrained optimization which is suited to integrated circuit (IC) design is presented and is shown to be additionally capable of the efficient generation of useful trade‐off information. In contrast to existing optimization methods in which the constraint functions are only linearized, the new algorithm employs a newly developed method of using optimization history data to obtain, without extra simulation, a second‐order approximation to both objective and constraint functions. In the new algorithm the search direction created at each optimization iteration is based on this second‐order approximation. As a result the computational efficiency has been greatly improved compared with other constrained optimization methods in terms of the number of function evaluations required, a measure which is crucial in the context of IC design. the effectiveness and efficiency of the new algorithm have been demonstrated by means of some numerical examples which are commonly employed as benchmarks for existing optimization methods and by several electronic circuit examples. In all cases encouraging results have been obtained. It is also demonstrated that the information generated during the last stage of the optimization allows the generation of accurate trade‐off information valid over a wide range of circuit perf

ISSN:0098-9886    

DOI:10.1002/cta.4490200308

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1992

数据来源: WILEY

摘要:

AbstractIdeal switches are rarely modelled in network analysis because inconsistent conditions can occur at the instant of switching. This causes standard integration routines to fail. If the initial conditions can be determined, the use of ideal switches can considerably speed up analysis and can make the results easier to understand. This paper, partly a review, presents a method which can handle ideal switching, inconsistent initial conditions, Dirac impulses and signals with discontinuities. It is applicable to networks containing linear or non‐linear element

ISSN:0098-9886    

DOI:10.1002/cta.4490200309

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1992

数据来源: WILEY

摘要:

AbstractAn analogue CAD tool capable of simulating MOS circuit performance variance caused by intra‐die variability inherent to IC fabrication processes has been developed. the nucleus of this tool is a general, CAD‐compatible, MOS statistical model called SMOS which comprehends the effects of device geometry, circuit layout and transistor bias on parameter variance. an example of the model calculation procedure is presented to illustrate both the modelling algorithms and the process characterization data required by the statistical model. the statistical model is verified through experimental data which show excellent agreement with performance variances predicted by simulation. Implementations of the statistical model in two circuit simulation environments, SPICE and APLAC, are also described. Statistical analysis and simulation of two basic analogue subcircuits, the current mirror and the source‐coupled pair, are pres

ISSN:0098-9886    

DOI:10.1002/cta.4490200310

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1992

数据来源: WILEY

ISSN:0098-9886    

DOI:10.1002/cta.4490200301

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1992

数据来源: WILEY