摘要:

The article describes what hardware accelerators are, what they can do, the way that they do it, possible limitations, possible alternatives, and some factors to be taken into account when considering the purchase of one of these machines.

DOI:10.1049/cae.1989.0020

出版商:IEE    

年代:1989

数据来源: IET

摘要:

With the advent of VLSI, many architectures have evolved for the viable implementation of hardware accelerators as a means of improving the performance of the CAD algorithms used in the design of VLSI circuits. These architectures, which include massively parallel machines, dataflow machines, vector processors etc., together with their application to CAD algorithms, are described in the paper.

DOI:10.1049/cae.1989.0021

出版商:IEE    

年代:1989

数据来源: IET

摘要:

A design or test engineer may proudly boast ‘I have a fault coverage of 96%’. What does he or she mean by that and how does it relate to yield in production or detection of system failures? The paper explains some basic concepts with regard to fault simulation and indicates the relationship between fault coverage and yield.

DOI:10.1049/cae.1989.0022

出版商:IEE    

年代:1989

数据来源: IET

摘要:

With the growing acceptance of simulation tools for the analysis and verification of digital circuits, and the ever increasing complexity of digital system designs involving multiple ASICs and complex commercial VLSI components, designers are demanding increased performance from the design tools. This paper outlines the problems associated with accelerating design verification tools focused for system-level design. The architecture of a commercially available general purpose hardware accelerator is then described to see how these problems can be addressed.

DOI:10.1049/cae.1989.0023

出版商:IEE    

年代:1989

数据来源: IET

摘要:

Today's workstations offer a significant performance acceleration compared with yesterday's general purpose computers, raising the question of whether there is a role for specialised hardware accelerators. The paper discusses this issue in the context of an engine developed by the Computer Science Department at Manchester University, for routing multilayer printed circuit boards. The accelerator has formed an essential part of the department's CAD facility for several years and a second generation machine has just been commissioned.

DOI:10.1049/cae.1989.0024

出版商:IEE    

年代:1989

数据来源: IET