摘要:

AbstractClusters of workstations connected by local area networks are in common use in many organizations. The combined processing power of these clusters is rarely exploited owing to the lack of suitable parallel algorithms. The paper describes a parallel programming paradigm calledsupervisor‐worker, suitable for the workstation environment, which can be used to speed up the execution of a large class of existing sequential programs. Simple formulae are developed to predict the speed‐up of a parallel algorithm developed in this way. The predictions depend on two easily‐determined parameters of the sequential program and the characteristic communication cost of the workstation cluster. Consequently, it is possible to estimate the benefits of the parallel program before proceeding with detailed implementation. As an example, the parallel version of a travelling salesman program is developed and the measured speed‐up compared with the predicted s

ISSN:0038-0644    

DOI:10.1002/spe.4380210302

出版商:John Wiley&Sons, Ltd.    

年代:1991

数据来源: WILEY

摘要:

AbstractDASH is a distributed operating system kernel. Message‐passing (MP) is used for local communication, and the MP system uses virtual memory ( VM) remapping instead of software memory copying for moving large amounts of data between virtual address spaces. Remapping eliminates a potential communication bottleneck and may increase the feasibility of moving services such as file services to the user level. Previous systems that have used VM remapping for message transfer, however, have suffered from high per‐operation delay, limiting the use of the technique. The DASH design reduces this delay by restricting the generality of remapping: a fixed part of every space is reserved for remapping, and a page's virtual address does not change when it is moved between spaces.We measured the performance of the DASH kernel for Sun 3/50 workstations, on which memory can be copied at 3·9 MB/s. Using remapping, DASH can move large messages between user spaces at a rate of 39 MB/s if they are not referenced and 24·8 MB/s if each page is referenced. Furthermore, the per‐operation delay is low, so VM remapping is beneficial even for messages containing only one page. To further understand the performance of the DASH MP system, we broke an MP operation into short code segments and timed them with microsecond precision. The results show the relative costs of data movement and the other components of MP operations, and allow us to evaluate several specific design de

ISSN:0038-0644    

DOI:10.1002/spe.4380210303

出版商:John Wiley&Sons, Ltd.    

年代:1991

数据来源: WILEY

摘要:

AbstractThe increasing availability and use of supercomputers has highlighted the need for better software development techniques and tools. Supercomputers have traditionally been extensively used by engineers and scientists whose preference for Fortran is well established and recognized. However, in the parallel environment offered by the latest configurations of supercomputers, more sophisticated languages and tools are required. The present experiment is concerned with devising a syntax‐directed integrated programming environment based on the language Actus, which enables a user to develop and debug programs before submitting them to an actual supercomputer. Actus is a high‐level, Pascal‐like language, with SIMD parallel processing features. It enables the user to ignore the idiosyncrasies of the chosen supercomputer by abstracting the parallel processing detail to a higher level. The editing, compilation and testing phases of program development are all integrated, providing a single consistent interface for all activities relating to program develo

ISSN:0038-0644    

DOI:10.1002/spe.4380210304

出版商:John Wiley&Sons, Ltd.    

年代:1991

数据来源: WILEY

摘要:

AbstractVertical migration is a widely acknowledged technique for improving the performance of critical sections of code. Migration may be to the assembly‐language level or, for machines with writable control store, into microcode. The former is easier to implement and allows a degree of portability, albeit limited, of the target routines, although performance gains may not be as great as those resulting from migration into microcode. The latter however, requires considerable programming effort and the size of available control store may well place restrictions upon the amount of code which can be migrated to this level. Given the task of improving the performance of a large software base, full migration is rarely practical, so time must be spent determining the best migration strategy for a ‘target set’ of critical routines.In this paper, we report on work to improve, by vertical migration, the performance of the bask linear algebra subroutines of the FORTRAN NAG library. We identify a number of different migration strategies based upon the availability of two migration levels and report on the performance gains achieved by applying each of these strategies; various conditions under which each strategy may be most appropriate have thus been identified. In particular, this work shows how, by careful selection of just a small number of target routines, resulting performance gains can not only be significant for each individual routine, but also for the whole software s

ISSN:0038-0644    

DOI:10.1002/spe.4380210305

出版商:John Wiley&Sons, Ltd.    

年代:1991

数据来源: WILEY

摘要:

AbstractThe performance of program‐derived combinator graph reduction is known to be superior to that of graph reduction based on a fixed set of standard combinators. The major advantage of program‐derived combinator reduction is that it uses less transient store than standard combinator reduction. We show on what activities a combinator reduction algorithm spends its execution time. Based on this analysis we show that it depends to a large extent on the application how much faster a program will run if program‐derived combinators are used instead of standard combinators. The analysis is based on experimental evidence obtained from a small bench‐mark of medium‐size functional programs. Performance gains of up to 11 x are reported for target architectures on which each memory reference consumes one unit of time. The results are valid for implementations of combinator graph reduction that use bina

ISSN:0038-0644    

DOI:10.1002/spe.4380210306

出版商:John Wiley&Sons, Ltd.    

年代:1991

数据来源: WILEY

摘要:

AbstractAs parallel machines become more widely available, many existing algorithms are being converted to take advantage of the improved speed offered by such computers. However, the method by which the algorithm is distributed is crucial towards obtaining the speed‐ups required for many real‐time tasks. This paper presents three parallel implementations of the Douglas—Peucker line simplification algorithm on a Sequent Symmetry computer and compares the performance of each with the original sequential algo

ISSN:0038-0644    

DOI:10.1002/spe.4380210307

出版商:John Wiley&Sons, Ltd.    

年代:1991

数据来源: WILEY

ISSN:0038-0644    

DOI:10.1002/spe.4380210301

出版商:John Wiley&Sons, Ltd.    

年代:1991

数据来源: WILEY