摘要:

After patterning the Platinum/crystalline SrBi2Ta2O9bilayer by Argon based Reactive Ion Etching (RIE), a degradation of the remanent polarization and leakage current of the capacitors for smaller feature sizes is observed. To simulate the study of the side wall of the capacitors, etching of blanket SBT is used as a model experiment. It is shown that etching of crystalline SBT is damaging the SBT material, resulting in the formation of small crystallites (SEM), the appearance of an unknown peak (XRD) and reduction of the Bismuth content on the SBT surface (AES). Using non-crystalline SBT, neither a degradation of electrical properties for smaller feature sizes nor a structural damage of blanket SBT is found after etching and recrystallization annealing although after etching of non-crystalline SBT also a loss of Bi is seen as indicated by AES. Therefore the following model is proposed: Patterning the Pt/crystalline SBT capacitor leads to a Bi deficient edge of the dielectric. Due to the crystalline SBT, this damaged zone can not be recovered by the final recovery anneal. For the non-crystalline SBT however, the Bi deficient regions at the edge are recovered during final anneal by the crystallizing SBT material itself.

ISSN:1058-4587    

DOI:10.1080/10584589908228470

出版商:Taylor & Francis Group    

年代:1999

数据来源: Taylor

摘要:

We report the effect of top electrode structure on the electrical properties of ferroelectric Pb(ZrxTi1-x)O3(PZT) capacitors. Samples with Ir/PZT/Ir or Ir/IrO2/PZT/Ir stacks were prepared using reactively sputtered Ir/IrO2(top) and Ir (bottom) electrodes and MOCVD-deposited PZT on TiAIN/SiO2/Si wafers. Capacitor structures were patterned by plasma etching of the top electrode and show evidence for transient fence formation. Electrical measurements of the capacitors showed good ferroelectric properties (2Prup to 38 μC/cm2, with leakage <10−6A/cm2) and low fatigue (<20% drop in Qsw) out to 8×1010cycles. Samples with top electrode structures containing IrO2gave higher 2Prvalues and lower pre-anneal fatigue, when compared with Ir-only top electrode samples. The sample with top electrode containing the thinnest IrO2layer showed slightly lower fatigue than the rest. We also briefly describe the use of these structures and etch methods in fabricating backend-integrated ferroelectric capacitors.

ISSN:1058-4587    

DOI:10.1080/10584589908228471

出版商:Taylor & Francis Group    

年代:1999

数据来源: Taylor

摘要:

Ferroelectric thin films for memory and MEMS applications require noble metal or refractory metal oxide electrodes. In this paper, physical and chemical mechanisms during platinum etching by a dual frequency ECR/RF reactor have been investigated. An ion beam was generated by means of a 50 mm diameter ECR-gun directed towards the substrate. The latter was placed on a RF powered electrode for discharging and local activation of reactive gas species. The removal characteristics of blanket platinum films and platinum films with a patterned mask (photoresist or SiO2masks) were investigated as a function of gas chemistry (Ar, halogen gases), ion beam energy (ion extraction/acceleration voltages), substrate bias RF power and working pressure (from 5 × 10−3Pa to 5 × 10−1Pa). The platinum etch process was characterized in terms of etch rate, selectivity, critical dimension, lateral uniformity and mask stability. A high rate etching processes (up to 100 nm/min with SiO2mask and 25 nm/min with removable photoresist) were obtained for micron scale patterns. Patterning of a complete layer stack PZT/Pt/SiO2could be achieved with a single photolithography step.

ISSN:1058-4587    

DOI:10.1080/10584589908228472

出版商:Taylor & Francis Group    

年代:1999

数据来源: Taylor

摘要:

A 1T/2C FeRAM cell technology for high density applications is firstly discussed. 1T/2C FeRA cell with Vcc/2 reference voltage level has been successfully developed for high stable operation of FeRAMs. This structure is promising for high density FeRAMs. This paper also describes CMVP memory cell which is suitable for high performance CMOS logic embedded FeRAM. A PZT capacitor was firstly formed on metal(Al)/via(W) stacked plug using low-temperature MO-CVD process. CMVP memory cell is a candidate of embedded FeRAM in the future.

ISSN:1058-4587    

DOI:10.1080/10584589908228473

出版商:Taylor & Francis Group    

年代:1999

数据来源: Taylor

摘要:

This study seeks to determine the feasibility and suitability of SBTN as a ferroelectric material used in the semiconductor wafer fabrication process. While Ramtron has years of experience producing PZT based parts, one vision for the future is that different materials may be required for different applications, depending on the specific product requirements. The family of bismuth layered perovskites may provide a path to low voltage applications, if the problems related to process integration and manufacturing that cause low bit count failures can be controlled. The design, manufacturing process and assembly are described, then a detailed evaluation is undertaken regarding retention performance.

ISSN:1058-4587    

DOI:10.1080/10584589908228474

出版商:Taylor & Francis Group    

年代:1999

数据来源: Taylor

摘要:

A ferroelectric random access memory (FeRAM) was fabricated using a novel processing technology to investigate the characteristics of the FeRAM with a new cell structure. The new cell includes two split word lines (SWL's) which play roles not only as word lines but also as plate lines. This structure can enhance operation speed and prevent the decrease of remnant polarization of non-selected cell capacitors in write/read operation since SWL's can be driven independently. The cell capacitors were composed of Pt electrodes and the sol-gel derived Pb(Zr,Ti)O3films. An efficient procedure to realize the new cell structure is proposed by introducing a new etching method, which includes the one-step patterning of a metal-ferroelectric-metal (MFM) and a metal-ferroelectric (MF) using a metal mask (Ti or Ru) and an etch stopping layer (TiO2or RuO2). The degradation of the ferroelectric capacitors due to etching process and interlayer dielectric (ILD) deposition process was almost recovered by annealing in oxygen. Memory operation was confirmed in the 2T/2C SWL FeRAM with the capacitor area down to 16 μm2.

ISSN:1058-4587    

DOI:10.1080/10584589908228475

出版商:Taylor & Francis Group    

年代:1999

数据来源: Taylor

摘要:

High performance LSIs embedded with ferroelectric random access memory (FeRAM) for contactless IC cards are now commercially available. The emphasis is placed on the materials solution with SrBi2(Ta,Nb)2O9(SBTN) which enables to exploit the potential performance of FeRAMs for composite logic/microcontroller LSIs operating at high speeds and low powers. The leading-edge 0.6-μm and double-level-metal FeRAM technology produces microcontroller-embedded LSIs with 14-kbit or 64-kbit FeRAM. A mature 0.8-μm and single-level-metal process has been built to maximize the die yield. Yields exceeding 90% indicate the excellent process stability. Product qualification data have proven the robust FeRAM technologies.

ISSN:1058-4587    

DOI:10.1080/10584589908228476

出版商:Taylor & Francis Group    

年代:1999

数据来源: Taylor

摘要:

One of the prevailing concerns regarding the PLZT based system has been in its scalability for low voltage operation. Through process enhancements, a sputtered PLZT film with Calcium and Strontium dopants, has been optimized on a platinum electrode system and scaled for low voltage operation. This paper will present general background data covering the optimization of the Ferroelectric film and SOIC “Plastic” package results for a fully integrated 64k FRAM® incorporating this film.

ISSN:1058-4587    

DOI:10.1080/10584589908228477

出版商:Taylor & Francis Group    

年代:1999

数据来源: Taylor

摘要:

FRAM® Memory Products manufactured by Ramtron International Corp., which are currently in mass production use the 2T2C cell architecture. For the correct and reliable operation of this 2T2C FRAM® memory, it is very critical that the sense amplifiers are well balanced. Any imbalance in the sense amplifiers would cause a data state preference and lead to data retention or functional failures that would compromise the yield and reliability of the product. It is very possible that inherent sense amplifier imbalances will not show up till the switching in the ferroelectric capacitors has been sufficiently degraded due to extended bakes or other stress conditions. This could lead to a scenario where these inherent sense amplifier imbalance issues are not comprehended till the product is well into its production build and qualification process. In a mass production and timeline driven project this is not an acceptable situation. This paper will discuss a simple andpatentedtesting technique at wafer level that allows us to quickly characterize any data state preference issues without having to subject the wafers to long stress conditions. This paper will also discuss how this test method has been very successful in correlating imbalance and data state preference issues seen at wafer level to that seen on the final packaged product.

ISSN:1058-4587    

DOI:10.1080/10584589908228478

出版商:Taylor & Francis Group    

年代:1999

数据来源: Taylor

ISSN:1058-4587    

DOI:10.1080/10584589908228449

出版商:Taylor & Francis Group    

年代:1999

数据来源: Taylor