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1. |
A modified objective function and a fast algorithm for design centering |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 129,
Issue 4,
1982,
Page 110-114
D.Agnew,
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摘要:
For a class of methods using minimax optimisation for design contering, a new objective function is proposed which gives improved performance. Then, a simplified approximate method of the same class is developed, using the new objective function and using a Taylor-series expansion to estimate the worst-case network response. Examples based on practical networks are given, which demonstrate that good results can be obtained using the algorithm described.
DOI:10.1049/ip-g-1.1982.0022
出版商:IEE
年代:1982
数据来源: IET
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2. |
An unconstrained nonlinear programming approach to design centering |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 129,
Issue 4,
1982,
Page 115-121
FinnAidt,
HansGaunholt,
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摘要:
An algorithm for design centering linear electic networks with fixed tolerances is descibed. By assuming a linear relationship between the statistical deviations of the component values and the circuit response, an objective function based on failure probabilities – the probabilities of violating specifications at the individual frequencies – is introduced. The objective function is minimised by unconstrained optimisation in a least-squares or minimax sense. Although applications of the method at present are limited to problems where the errors introduced by the above linear relationship are reasonably small, the method has several advantages which rely on its deterministic foundation. For instance, it is easy to implement facilities which enable the designer to consider tracking variables and constrain toleranced variables not to change value during optimisation. Examples demonstrate applications of the method to small as well as large circuits, and, finally, proposals for improvement of the method are considered.
DOI:10.1049/ip-g-1.1982.0023
出版商:IEE
年代:1982
数据来源: IET
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3. |
Yield enhancement realised for analogue integrated filters by design techniques |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 129,
Issue 4,
1982,
Page 122-126
KarlKnauer,
Hans-JörgPfleiderer,
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摘要:
In the fabrication of analogue integrated circuits the yield depends on the tolerances and defect density in mask generation and device fabrication. Yield optimisation, therefore, has to resolve two conflicting requirements. Whereas to reduce the influence of tolerances the device area has to be large, the larger the device area chosen, the higher will be the possible defect number. To determine the optimum device area with respect to yield in the fabrication of CCD transversal filters, the tolerances in mask generation and fabrication have first to be analysed. Tolerances that are constant in a device can be eliminated by ‘design cleverness’. The way in which the influence of statistical tolerances can be reduced by design centering will be demonstrated with reference to an implemented device. To determine the total yield it is further necessary to take into account the influence of defects. The optimum device area from the aspect of yield can then be determined as a function of both tolerance and defect density.
DOI:10.1049/ip-g-1.1982.0024
出版商:IEE
年代:1982
数据来源: IET
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4. |
Estimating manufacturing yield by means of Jacobian of transformation |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 129,
Issue 4,
1982,
Page 127-133
A.S.Cook,
T.Downs,
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摘要:
It has been known for many years that the Jacobian of transformation method could, at least in principle, be applied to the yield estimation problem. The fact that it has not, in the past, been applied to this problem is because its implementation requires the determination of multiple solutions to nonlinear equations. Recently, several methods of finding multiple solutions to nonlinear equations have appeared in the literature, and in this paper it is shown how these methods can be used in conjunction with the Jacobian of transformation method in order to estimate manufacturing yield. As a technique for yield calculation, the method is found to be generally inferior to Monte Carlo simulation. Some approaches to improving the efficiency of the technique are described, but the improvements do not allow the technique to approach the efficiency of Monte Carlo. The technique does, however, have attributes which indicate that it could be a useful tool in statistical design. These attributes are discussed in the paper.
DOI:10.1049/ip-g-1.1982.0025
出版商:IEE
年代:1982
数据来源: IET
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5. |
Design centering and tolerancing, considering environmental effects via a new type minimax optimisation |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 129,
Issue 4,
1982,
Page 134-138
EdithHalász,
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摘要:
A method for design centering and tolerancing of tuned circuits, subject to environmental disturbances, is described. The region of acceptability is explored statistically, using a new method of gradient-based minimax optimisation with randomly chosen initial points. Nominal values and tolerances of continuous or discrete valued elements are determined from historgrams, which are built up from the analytical data collected during the exploration process. The method is illustrated by the design of two lossy, tunedLCladder filters.
DOI:10.1049/ip-g-1.1982.0026
出版商:IEE
年代:1982
数据来源: IET
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6. |
A sensitivity-based approach to tolerance assignment |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 129,
Issue 4,
1982,
Page 139-149
AjokellIlumoka,
RobertSpence,
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摘要:
A new and efficient algorithm is described for selecting the most economic set of component tolerances for a mass-produced electronic circuit, and is illustrated by application to two filter circuits. The algorithm is based on a statistical sampling of component space, and its efficiency is a consequence of using inexpensive sensitivity information to calculate response from a truncated Taylor-series approximation. The algorithm extends, to tolerance space, the familiar concept of undertaking exploratory random perturbations in order to seek an optimum design. The computational cost of the algorithm is shown to be reasonable: moreover, theoretical considerations and experimental evidence indicate the likelihood of further considerable reduction in the computational cost of tolerance assignment.
DOI:10.1049/ip-g-1.1982.0027
出版商:IEE
年代:1982
数据来源: IET
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7. |
Tolerance design via cost minimisation |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 129,
Issue 4,
1982,
Page 150-159
N.Maratos,
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摘要:
A new method is described for the tolerance design of circuits, via minimisation of a cost function of the yield and tolerances. This problem is decomposed into the simpler problems of design centring with fixed tolerances, and tolerance assignment by efficient nonlinear optimisation based on a nonlinear approximation of the yield/tolerance dependence. Two algorithms are proposed, and their performance is evaluated on numerical examples.
DOI:10.1049/ip-g-1.1982.0028
出版商:IEE
年代:1982
数据来源: IET
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8. |
Generalised cut map algorithms for tolerance and tolerance-tuning problems |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 129,
Issue 4,
1982,
Page 160-168
AlexanderVoreadis,
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摘要:
The problem considered is the choice of a set of system parameters, so that inequality constraints are satisfied or can be satisfied by tuning, for a specified variation of parameter values about their nominal value. Such problems occur when systems must be synthesised from components whose values are known only to certain tolerances. Fully implementable algorithms that are suitable for the general nonconvex cases and utilise concepts employed by Eaves and Zangwill in their generalised cutting plane algorithms are presented. The algorithms generalise earlier algorithms for the pure tolerance (no tuning) and the tolerance-tuning problems that are suitable only for the case when the tolerance and tuning regions are constant.
DOI:10.1049/ip-g-1.1982.0029
出版商:IEE
年代:1982
数据来源: IET
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9. |
Variability reduction: statistically based algorithms for reduction of performance variability of electrical circuits |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 129,
Issue 4,
1982,
Page 169-180
AjokeIlumoka,
NicholasMaratos,
RobertSpence,
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摘要:
A number of algorithms are presented for the reduction of circuit-response variability arising from component tolerances. A Monte Carlo analysis is carried out in the tolerance region and the responsesFand differential response sensitivities ∂F/∂piwith respect to circuit parameterspcalculated at each sample point. This enables both the variance of the responses and the circuit yield over the tolerance region to be estimated. At a given iteration, a descent direction for variance is determined by one of a number of different methods, and a suitable step length for the movement of the nominal point calculated. These two operations make extensive use of linear approximations to the response for the estimation of variance and yield for known displacements in the circuit parameters. As a consequence, the method is very efficient (∂F/∂piare inexpensive to compute), since the number of fresh circuit analyses is kept to a minimum.
DOI:10.1049/ip-g-1.1982.0030
出版商:IEE
年代:1982
数据来源: IET
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10. |
Specification sensitivity and its use in system design |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 129,
Issue 4,
1982,
Page 181-185
L.Gefferth,
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摘要:
An algorithm is described which computes the sensitivity of the manufacturing yield of a circuit or a system with respect to changes in the specifications. Using the concept of specification sensitivity, the change of the yield due to different changes of the specifications can be calculated without performing a new Monte Carlo analysis or retesting the network function. Circuits designed to work under environmental influence have to be tested at the production stage against a production specification, which also can be determined by specification sensitivity.
DOI:10.1049/ip-g-1.1982.0031
出版商:IEE
年代:1982
数据来源: IET
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