1. |
Probability machines and shift-register sequence segmentation |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 134,
Issue 5,
1987,
Page 209-215
J.J.Narraway,
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摘要:
A basic multiprocessor probability machine is described. If a shift register is used to generate random numbers for such a machine, it becomes necessary to be able to find the state of the shift register at points part way along the available number sequence. Methods are described for accomplishing this segmentation.
DOI:10.1049/ip-g-1.1987.0030
出版商:IEE
年代:1987
数据来源: IET
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2. |
Efficient bit-level systolic array for the linear discriminant function classifier |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 134,
Issue 5,
1987,
Page 216-224
C.-L.Wang,
C.-H.Wei,
S.-H.Chen,
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摘要:
The linear discriminant function classifier is a widely used but computationally demanding method in statistical pattern recognition. This paper describes a bit-level systolic array for the linear discriminant function classifier to improve its processing speed. The system includes a new scheme for inner product computation, which not only has 100% efficiency but also gains a speed improvement over a previous method, and yields classification results at an average rate of one perBcycles of the array, whereBis the wordlength of the input data. The throughput is higher than those of the related bit level arrays described previously.
DOI:10.1049/ip-g-1.1987.0032
出版商:IEE
年代:1987
数据来源: IET
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3. |
Generalised maximally flat approximation |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 134,
Issue 5,
1987,
Page 225-228
M.de P.Barros,
L.F.Lind,
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摘要:
An analytical method to generalise the classical Butterworth approximation into a maximally flat approximation function possessing finite and asymmetric transmission zeros is presented. The passband of this general function is no longer restricted to the usual − 3 dB at ±1 rad/s coordinates, and therefore extremely asymmetric characteristics can be generated, such as those required by pseudohighpass or pseudolowpass filters. The final network realisation can be conveniently absorbed into narrowband crystal filter design techniques. Two examples are given.
DOI:10.1049/ip-g-1.1987.0033
出版商:IEE
年代:1987
数据来源: IET
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4. |
Large-signal frequency responses of 2nd-order filters containing multiple amplifiers |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 134,
Issue 5,
1987,
Page 229-235
A.S.S.Al-Kabbani,
P.Bowron,
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PDF (684KB)
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摘要:
The describing-function technique is extended to predict the large-signal performance of active filters containing any number of operational amplifiers. This is achieved by generalising the theory of active filters whose amplifiers are each represented by a dominant pole and a saturation nonlinearity. As examples, the jump-resonance amplitude and phase characteristics of several popular 3-amplifier 2nd-order bandpass filter circuits are then evaluated and compared. The conditional-stability problem appears to be more severe than for single- and double-amplifier filters.
DOI:10.1049/ip-g-1.1987.0034
出版商:IEE
年代:1987
数据来源: IET
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5. |
Novel floating negative immittance convertor |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 134,
Issue 5,
1987,
Page 236-238
R.Nandi,
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摘要:
A network realisation for a floating negative immittance convertor (FNIC) using second generation current conveyor (CCII) elements has been proposed. The novelties of the scheme are no design constraints involving matched components, use of only the nominal termination component with ideal CCII devices. Even with nonideal but matched devices, a true FNIC realisation does not require any additional component matching. With nonideal and unmatched devices, a precise bilateral FNIC is realisable simply by connecting a single compensating component appropriately. The sensitivities of the elements of the [Y] matrix relative to active device deviations have been shown to be extremely low. A network synthesis application of the FNIC has also been suggested.
DOI:10.1049/ip-g-1.1987.0035
出版商:IEE
年代:1987
数据来源: IET
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6. |
Phase detector performance in the presence of harmonic distortion |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 134,
Issue 5,
1987,
Page 239-242
J.Siuzdak,
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PDF (358KB)
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摘要:
The influence of harmonic distortion on phase errors is investigated. Linear (saw-tooth), triangular and sinusoidal phase detectors are examined. It is shown that these errors are directly related to the harmonic distortion factors of the input signals. The errors are computed for each phase detector.
DOI:10.1049/ip-g-1.1987.0036
出版商:IEE
年代:1987
数据来源: IET
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7. |
Delay estimate in a capacitively loaded URC line |
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IEE Proceedings G (Electronic Circuits and Systems),
Volume 134,
Issue 5,
1987,
Page 243-245
J.M.Zurada,
T.Liu,
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PDF (257KB)
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摘要:
An approximated solution for the delay time of an open-ended uniformly distributedRC(URC) line has been developed. An estimate of the delay time for a capacitively loaded URC line has been derived. The results obtained may be useful for delay simulation in VLSI interconnections.
DOI:10.1049/ip-g-1.1987.0037
出版商:IEE
年代:1987
数据来源: IET
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