摘要:

Knowledge of the electrical failure modes and of the physical mechanisms that cause faults is fundamental to implementing realistic fault models. Therefore, failure physics is the basis of effectual test sequence generation, and can give guidelines also for the design of testable and reliable integrated circuits. In the paper the failure modes and mechanisms of complex integrated circuits are reviewed. Faults are classified with respect to their allocation in the devices. Bulk defects, and failures in the dielectric layers, metallisation and package interconnections are then examined. Special attention is devoted to failures spurred by the reduction of dimensions for VLSI (‘scaling’)

DOI:10.1049/ip-g-1.1985.0018

出版商:IEE    

年代:1985

数据来源: IET

摘要:

VLSI circuits currently being designed are so complex that it is now extremely difficult to test them adequately to determine whether or not they have been processed correctly. Design for testability (DFT) techniques are often used in an attempt to ease this problem by identifying and redesigning potentially ‘difficult-to-test’ parts of the circuits. The ‘testability’ of the circuit is usually evaluated in terms of the stuck-at fault model. However, there have been growing doubts over the ability of this model to cover certain common faults that can occur in MOS processing (at present, the dominant VLSI technology). The paper describes software simulations of faults in simple NMOS logic circuits showing that not all fault effects in NMOS circuits are modellable as ‘stuck’ nodes. An improved fault model which would better reflect MOS fault effects has yet to be defined. Until such an improved model is available, DFT rules for MOS circuits are best regarded as provisional. We therefore conclude with a discussion ofad hoc‘physical design for testability’ techniques that exploit current understanding of the relation between MOS faults and their fault effects.

DOI:10.1049/ip-g-1.1985.0019

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The UK5000 project has produced a 5000-gate CMOS array, together with a design automation system that automates its production. The array uses a combination of design rules built into the silicon layout and software tools. Together these make it very easy for the array users to design chips that are very testable and free from timing hazards.

DOI:10.1049/ip-g-1.1985.0020

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The paper presents a system of random pattern/signature analysis self-test in NMOS bit-serial signal processing chips, designed by a silicon compiler. Fault coverage is very high, and is determined without full fault simulation. A trial design shows that the cost in silicon, power, complexity and design difficulty is extremely low. A hierarchical system test can be performed, thus permitting fault tolerance. A dynamic CMOS design style supersedes that of the NMOS bit-serial cells. The problem of generating tests for stuck-open faults is removed. This is proved analytically and fault simulation results are presented.

DOI:10.1049/ip-g-1.1985.0021

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The paper contains the results of an experiment which observes the capabilities of a linear feedback shift register network, to both generate pseudorandom test patterns and compress the results of a test. Two typical networks from an actual LSI designed machine are used.

DOI:10.1049/ip-g-1.1985.0022

出版商:IEE    

年代:1985

数据来源: IET

摘要:

One view of what constitutes a testable circuit design is that sufficient circuit knowledge exists to allow an effective test program to be generated. HITEST is a test-generation system based on the definition, capture and use of knowledge items about the elements and overall behaviour of the circuit. The paper describes the general form of the knowledge items and indicates how the system makes use of and is constrained by the knowledge.

DOI:10.1049/ip-g-1.1985.0023

出版商:IEE    

年代:1985

数据来源: IET