摘要:

The simplicial approximation approach to design centering1is based on developing a polyhedral approximation to the feasible region in the parameter space. Although the original method has been modified so as to allow arbitrary statistical distributions,2it still becomes computationally expensive as the dimension of the parameter space becomes large. In this paper, a technique is proposed for reducing the dimension of the parameter space and thereby significantly increasing the size of the circuit for which the simplicial approximation approach can be applied. This technique is particularly useful in integrated circuit applications where strong correlations between circuit elements exist, and the number of circuit elements can be large.

DOI:10.1049/ip-g-1.1980.0044

出版商:IEE    

年代:1980

数据来源: IET

摘要:

This paper addresses the problem of design centering; that is, the maximisation of manufacturing yield by suitable choice of nominal component parameter values while the tolerances and form of the probability density function of the parameters are assumed fixed. In the technique discussed, Monte Carlo analysis is performed for a particular set of nominal values. The results of the analysis are then used both to estimate yield and to choose new nominal values which are expected to increase yield. The procedure is repeated until no further increases in yield occur. The heuristic algorithm employed is based on the relative positions, in component space, of the centres of gravity of the pass and fail circuits as identified by the Monte Carlo analysis. The effectiveness of the procedure is illustrated for a number of circuit examples ranging from seven to forty-three toleranced components. Experience strongly suggests that the number of iterations required is independent of dimensionality (the number of toleranced components). Unlike other methods of design centering, the method does not require assumptions regarding the convexity or connectivity of the region of acceptability. Finally, to moderate the computational cost of iteratively performing Monte Carlo analysis, special sampling schemes are employed which reduce the number of sample circuits required to be analysed by each Monte Carlo analysis.

DOI:10.1049/ip-g-1.1980.0045

出版商:IEE    

年代:1980

数据来源: IET

摘要:

Two algorithms for centering and tolerancing networks are described. Both use first-order sensitivities to characterise network behaviour. Margin sensitivities are introduced as a simple measure of the likelihood that changes in components will cause specifications to be violated, based on first-order sensitivities. This new measure is used as the basis of the two algorithms. The first uses minimax optimisation in a ‘fixed tolerance’ centering procedure, while the second uses a minimum cost formulation of the problem and a scalar minimisation procedure. Examples demonstrate the effectiveness of the methods.

DOI:10.1049/ip-g-1.1980.0046

出版商:IEE    

年代:1980

数据来源: IET

摘要:

The paper describes a new method, using second derivatives, for the solution of a set of nonlinear simultaneous equations. Results of its application to equations arising from a transistor modelling problem are given and compared with the results obtained by other methods in common use, thereby demonstrating those areas in which use of the new method is likely to be beneficial.

DOI:10.1049/ip-g-1.1980.0047

出版商:IEE    

年代:1980

数据来源: IET

摘要:

Linear signal processing systems consisting of time-invariant circuits and carrier-actuated modulators are widely used. An analysis program, PAMS, developed specifically for such systems, and its application for design and analysis (including sensitivity studies) is discussed. Two application examples are given: namely (a) the variation of a single design parameter is shown to vary the response of a two-path filter from that of a lowpass to that of a bandpass filter, and the variation of a hardware parameter is shown to produce ‘forbidden’ output frequencies; and (b) two versions of a quadrature modulation-type vestigial sideband system are analysed; the suitability of two different filtering symmetry conditions is demonstrated, but the sensitivity of the system amplitude and phase responses to carrier-phase errors is shown to depend on the symmetry condition chosen.

DOI:10.1049/ip-g-1.1980.0048

出版商:IEE    

年代:1980

数据来源: IET

摘要:

The concept of nested macromodels is introduced to take advantage of the structural properties of large-scale integrated circuits. A multilevel algorithm for the analysis of circuits contanining nested macro-models is presented and its implementation is discussed.

DOI:10.1049/ip-g-1.1980.0049

出版商:IEE    

年代:1980

数据来源: IET

摘要:

A new scheme for macromodelling digital elements in the time domain is presented. Output waveforms and timing performances are predicted in detail, within an accuracy margin that depends mainly on the information available to describe the elements. A number pair (state, time-in-state) describe each individual element and, along with the macromodel of the element type, retain the necessary data to analyse the element at each time point. MASCOT (MAcro Simulator of Circuit Operation in the Time domain) is the set of programs incorporating the new concepts, and some results of analysis illustrate its use. Comparisons of run time between the new program and circuit-level simulators showed improvements of between two and three orders of magnitude.

DOI:10.1049/ip-g-1.1980.0050

出版商:IEE    

年代:1980

数据来源: IET

摘要:

Backtracking allows a routing program to erase a track if it is blocking other connections; the erased track can then be rerouted at a later stage. This technique is investigated in the paper and compared with conventional methods. Backtracking can lead to program looping, which in this case is avoided by using two types of track, ‘permanent’ and ‘provisional’. Provisional nodes and edges may be erased at later stages but not permanent.Routing programs using backtracking are likely to be more complex and time consuming in execution, but to have a higher success rate in finding connections.A comparison is made in the paper between a router using an algorithm adapted to backtracking and a more conventional method using two passes. In the conventional router, the first pass is a simple heuristic and the second a full search using the Moore-Lee algorithm. Results from a selected set of printed-circuit board layouts show that a significant improvement in connection yield was obtained by the backtracking router, but at a cost of approximately four times the computer time.

DOI:10.1049/ip-g-1.1980.0051

出版商:IEE    

年代:1980

数据来源: IET

摘要:

Two algorithms are proposed for m.o.s.i.c. layout: corner-point co-ordinate calculation and circuit diagram reconstruction. A layout sketch, the geometrical roles and transistor channel dimensions are input data for the co-ordinate calculation. In the minimisation of chip area, difficulties posed by the many independent variables are overcome by solving two linear optimisation problems.

DOI:10.1049/ip-g-1.1980.0052

出版商:IEE    

年代:1980

数据来源: IET

摘要:

The POLIGON system (PO Layout system using Interactive Graphics ON line) is described. This is an interactive graphics system based on the GEC 4000 series computer developed at the PO Martlesham Research Centre, designed to be cost effective and as a general-purpose system;it has been in use since early 1979.

DOI:10.1049/ip-g-1.1980.0053

出版商:IEE    

年代:1980

数据来源: IET