摘要:

A branch decomposition approach for fault diagnosis in analogue circuits is presented. Two fault models for the fault simulation of operational amplifier circuits are also proposed. The method uses linear fault diagnosis (FD) equations based on Kirchhoff's current law and nodevoltage measurements under the desired current excitations. The circuit is divided into subnetworks and appropriate interconnections. The checking of the consistency of the FD equations using nominal element values and the measured node voltages leads to the location of the faults in the circuit. The procedure can be applied to linear or nonlinear circuits for the location of single and multiple faults. Demonstrative examples of passive and active circuits are given to show the effectiveness of the proposed method.

DOI:10.1049/ip-g-1.1987.0022

出版商:IEE    

年代:1987

数据来源: IET

摘要:

Although the usual methods of designing active filters through the inductance simulation and frequency dependent negative resistor (FDNR) approaches necessarily require active networks capable of simulating ideal inductors and ideal FDNRs, this paper describes network transformations which make it possible to incorporate even nonideal (lossy) simulated inductance and FDNR elements directly into the filter design. It is shown that the use of these transformations leads to novel filter configurations having many advantageous features. The proposed transformations also prove to be important tools for deriving new sinusoidal oscillator configurations which have properties which are not possible with known oscillator circuits and for providing new interpretations and insights into known oscillator circuits. Experimental results are given which confirm the validity of the theory.

DOI:10.1049/ip-g-1.1987.0023

出版商:IEE    

年代:1987

数据来源: IET

摘要:

This paper presents a new approach to designing finite impulse response (FIR) digital filters. The design algorithm is based on the least mean square (LMS) criterion in the time domain to calculate the filter coefficients using the weighted gain peak errors to adjust the LMS cost function. The filter responses are optimum in the sense that the maximum gain error is minimised. The design procedure accommodates the entire range of linear phase FIR filter specifications. The flexibility and optimality of the LMS approach is demonstrated with a wide variety of examples, including the classic extraripple, scaled extraripple and equiripple cases of linear phase and examples of nonlinear phase. To date the only two algorithms that have been able to design the full range of linear phase filters are based on the Cheby̅chev polynomial approach, namely Remez exchange and linear programming.

DOI:10.1049/ip-g-1.1987.0024

出版商:IEE    

年代:1987

数据来源: IET

摘要:

A scheme for computing the discrete Fourier transform (DFT) of a 2-dimensional systolic array processor is presented. The DFT algorithm is rewritten as a matrix based algorithm and mapped onto a 2-dimensional systolic array processor. The significance of this approach is that the total time required to complete anN-point DFT is 3√(N) +Ntime units (assuming that it takes one time unit to operate data in a processor element (PE)); the architecture features nearest neighbour interconnections (as opposed to spatially global interconnections); all PEs in the 2-dimensional systolic array processor are busy (as opposed to some processor arrays in which half of the PEs are idle while the other half are busy); results of DFT computations are pipelined out directly in the correct order (as opposed to some processors which require bit-reversal operation or data commutation during the computational process); and the matrix-matrix multiplication and the diagonal elements of the matrix-matrix-matrix product can be computed systolically on the 2-dimensional processor.

DOI:10.1049/ip-g-1.1987.0025

出版商:IEE    

年代:1987

数据来源: IET

摘要:

A computationally efficient technique for the design of multidimensional spherically symmetric recursive digital filters satisfying prescribed magnitude and constant group delay specifications is presented. The denominator and the numerator of the transfer function are designed separately. The former is used to approximate the group delay response and the latter is used to approximate the magnitude response. Moreover, this method also makes use of the symmetric conditions of the transfer function. Therefore the numbers of parameters and sample points required for the optimisation are greatly reduced. As a result, the amount of computation can be minimised and the convergence can also be improved. Such advantages are extremely significant for high order multidimensional filter design. Two examples of the 2-dimensional and one example of the 3-dimensional digital filter design are given to illustrate the proposed method. Comparisons with the results of other methods are also given.

DOI:10.1049/ip-g-1.1987.0026

出版商:IEE    

年代:1987

数据来源: IET

摘要:

The application of junction chargecoupled devices (JCCDs) within the concept of bitlevel systolic arrays is discussed. The extremely small basic memory cell and the low power dissipation of CCDs make it a candidate for bit-level systolic arrays if fast suitable logic functions can be realised. Junction charge-coupled logic (JCCL) provides a good solution to the large amount of local memory. The implicit regeneration of charge packets and the variety of logic functions are strong arguments for using junction CCDs. A JCCL inner-product step-processor is described.

DOI:10.1049/ip-g-1.1987.0027

出版商:IEE    

年代:1987

数据来源: IET

摘要:

The effect of pole zero pairing on the total capacitance of cascaded biquad SC filters is investigated. It is shown that significant reductions in total capacitance and hence corresponding reductions in silicon area are possible through optimal pole-zero pairing without causing significant degradations in filter performance.

DOI:10.1049/ip-g-1.1987.0028

出版商:IEE    

年代:1987

数据来源: IET

摘要:

Built in logic block observation (BILBO) has become one of the most widely accepted techniques for self-testing of complex digital ICs. This technique is based on grouping the storage elements of the circuit in the two registers which give this technique its name. A BILBO register has four functional modes: with each of the stages acting as independent registers; as a generator of pseudorandom sequences; as analyser of multiple-input signatures; and reset of all stages. For a BILBO register to perform these four functions correctly the feedback from its state to its first stage must satisfy certain conditions. First, the pseudorandom sequence that it generates must be of maximum length, i.e. it must run through all possible states except zero. Secondly, when it is acting as a parallel signature analyser the number of stages must be large enough for the error escape probability to be negligible. Normally the feedback of a BILBO register is linear. We propose the use of nonlinear feedback, through Exclusive-Nor gates, which conserves the properties of linear feedback and provides the advantage that the fourth functional mode, reset, serves as a seed for the other modes. Additional logic is not required and a seed does not have to be introduced from an external source.

DOI:10.1049/ip-g-1.1987.0029

出版商:IEE    

年代:1987

数据来源: IET