摘要:

A chain circuit of four‐junction logic gates consisting of all refractory junctions with niobium nitride (NbN)‐niobium (Nb) double‐layered electrodes has been fabricated with a 2.5‐&mgr;m minimum feature. A reactive ion etching technique has been used for patterning every layer such as junction electrodes, molybdenum resistors, and insulation layers. The minimum logic delay of 18 ps/gate has been obtained in the experimental circuit.

ISSN:0003-6951    

DOI:10.1063/1.94259

出版商:AIP    

年代:1983

数据来源: AIP