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51. |
Barrier layer formation onCoSi2surface byNH3plasma treatment |
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AIP Conference Proceedings,
Volume 418,
Issue 1,
1998,
Page 469-474
Mitsuru Sekiguchi,
Satoshi Ueda,
Tokuhiko Tamaki,
Shuichi Mayumi,
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摘要:
Al-CoSi2reaction at 430 °C is suppressed byNH3plasma exposure to theCoSi2surface before Al deposition. An amorphous 5nm-thick Co-Si-N-O layer formed with the plasma treatment preventsCo2Al9orCo4Al13formation during annealing. N is combined with Si at the surface, but presumably with Co inside of the Co-Si-N-O layer. This technology is useful to form barrier layers on the silicide layer at low temperatures.
ISSN:0094-243X
DOI:10.1063/1.54669
出版商:AIP
年代:1998
数据来源: AIP
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52. |
Diffusion barriers between Si and Cu |
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AIP Conference Proceedings,
Volume 418,
Issue 1,
1998,
Page 475-480
Hidetsugu Mori,
Junji Imahori,
Takeo Oku,
Masanori Murakami,
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摘要:
Thermally stable, thinW2N,TaN and TaC diffusion barrier layers between Cu and Si were developed by a radio-frequency sputter-deposition technique. TheW2N(8 nm),TaN(8 nm) and TaC(5 nm) barrier layers were found to prevent the Cu diffusion to Si after annealing at 600, 700 and 600 °C for 30 min, respectively. These barrier layers have potential as diffusion barrier layers used in ULSI devices. Diffusion mechanism of Cu in Si was studied by using by x-ray diffraction and high-resolution electron microscopy. ©1998 American Institute of Physics.
ISSN:0094-243X
DOI:10.1063/1.54670
出版商:AIP
年代:1998
数据来源: AIP
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53. |
Statistical evaluation of device-level electromigration reliability |
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AIP Conference Proceedings,
Volume 418,
Issue 1,
1998,
Page 483-494
M. Gall,
C. Capasso,
D. Jawarani,
R. Hernandez,
H. Kawasaki,
P. S. Ho,
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摘要:
A new test structure for electromigration failure analysis of via-interconnect metallization schemes was developed. The new ensemble of via-interconnect structures can be wire-bonded within the test chip using different configurations thus selecting the number of vias under test. The correlation of the experimental data for different numbers of vias with the results of numerical simulation allows a better insight on the statistical properties of the failure mechanism. The new testing procedure allows extrapolation to operating conditions at the device level with tighter confidence intervals. Furthermore, critical length effects were investigated using many-via chain test structures with different interconnect lengths in drift-velocity type experiments. At interconnect lengths close to the critical Blech-length, resistance saturation effects were encountered and used for calculations of the criticalcurrent⋅lengthproduct,(jl)*.©1998 American Institute of Physics.
ISSN:0094-243X
DOI:10.1063/1.54671
出版商:AIP
年代:1998
数据来源: AIP
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54. |
A statistical approach to electromigration design for high performance VLSI |
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AIP Conference Proceedings,
Volume 418,
Issue 1,
1998,
Page 495-504
John Kitchin,
T. S. Sriram,
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摘要:
Statistical Electromigration Budgeting (J. Kitchin,1995 Symposium on VLSI Circuits) or SEB is based on the concepts: (a) reliable design in VLSI means achieving a chip-level reliability goal and (b) electromigration degradation is inherently statistical in nature. The SEB methodology is reviewed along with results from recent high performance VLSI designs. Two SEB-based approaches for efficiently coupling metallization reliability statistics to design options are developed. Allowable-length-at-stress design rules communicate electromigration risk budget constraints to designers without the need for sophisticated CAD tools for chip-level interconnect analysis. Electromigration risk contours allow comparison of evolving metallization reliability statistics with design requirements having multiple frequency, temperature, and voltage options, a common need in high performance VLSI product development. ©1998 American Institute of Physics.
ISSN:0094-243X
DOI:10.1063/1.54672
出版商:AIP
年代:1998
数据来源: AIP
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55. |
Chip-level electromigration reliability considering the statistical distribution of via stress conditions |
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AIP Conference Proceedings,
Volume 418,
Issue 1,
1998,
Page 505-516
Kazunori Hiraoka,
Yasuyuki Ito,
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PDF (405KB)
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摘要:
This paper describes a statistical approach to designing and predicting chip-level electromigration reliability. Reliability requirement for interconnects is designed using a statistical series model. Signal-line vias separated by long distances are shown to have the minimum failure time in interconnects. Statistical distributions of neighboring-via distance and current flow probability in a signal line indicate that only 0.3&percent; of vias have the possibility of electromigration failure. Computer simulation shows that chip-level failure times are approximately expressed by the Weibull distribution, even if the failure time of each via in a chip follows the lognormal distribution. The decrease in the number of significant vias results in longer times to the chip-level failure and increased allowable current density for circuit design. ©1998 American Institute of Physics.
ISSN:0094-243X
DOI:10.1063/1.54673
出版商:AIP
年代:1998
数据来源: AIP
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