摘要:

Transistor action was experimentally observed by John Bardeen and Walter Brattain in n‐type polycrystalline germanium on December 16, 1947 (and subsequently polycrystalline silicon) as a result of the judicious placement of gold‐plated probe tips in nearby single crystal grains of the polycrystalline material (i.e., the point‐contact semiconductor amplifier, often referred to as the point‐contact transistor).The device configuration exploited the inversion layer as the channel through which most of the emitted (minority) carriers were transported from the emitter to the collector. The point‐contact transistor was manufactured for ten years starting in 1951 by the Western Electric Division of AT&T. Thea priorituning of the point‐contact transistor parameters, however, was not simple inasmuch as the device was dependent on the detailed surface structure and, therefore, very sensitive to humidity and temperature as well as exhibiting high noise levels. Accordingly, the devices differed significantly in their characteristics and electrical instabilities leading to “burnout” were not uncommon. With the implementation of crystalline semiconductor materials in the early 1950s, however, p‐n junction (bulk) transistors began replacing the point‐contact transistor, silicon began replacing germanium and the transfer of transistor technology from the lab to the lab accelerated. We shall review the historical route by which single crystalline materials were developed and the accompanying methodologies of transistor fabrication, leading to the onset of the Integrated Circuit (IC) era. Finally, highlights of the early years of the IC era will be reviewed from the 256 bit through the 4M DRAM. Elements of IC scaling and the role of Moore’s Law in setting the parameters by which the IC industry’s growth was monitored will be discussed. © 2003 American Institute of Physics

ISSN:0094-243X    

DOI:10.1063/1.1622451

出版商:AIP    

年代:1903

数据来源: AIP

摘要:

Silicon (Si) transistor and integrated circuit (IC) technology has grown so big, and become so important, that it is now hard to recognize where, apart from the invention of the transistor itself (Bardeen and Brattain, Dec 16, 1947), it had its origin. In spite of obvious differences in Ge and Si, in 1950–55 it was not evident in many laboratories, concentrating only on Ge, what form of Ge transistor (grown, alloyed, jet‐etched, etc.) might be expected to prevail, with Si not even being considered (or being dismissed outright). What was the need for Si and, at the time, such a seemingly intractable peculiar new technology? The requirement on switching devices of low leakage, and thus the need to leave Ge in favor of Si, led directly in 1954–55 (Bell Telephone Laboratories, BTL) to the exploration of impurity‐diffusion and metallization technology to realize Si transistors and p‐n‐p‐n switches. This technology, a more or less ideal thin‐layer technology that can be referenced from a single surface (and which indeed has proven to be basically invariant and constantly growing), led further to the discovery (1955) of the protective Si oxide, oxide masking and patterning, and the fundamental basis of the integrated circuit (i.e., device‐to‐device interconnection by patterned metallization across the oxide). We recount some of the exploratory diffused‐impurity Si device development of 1954–55 at BTL, particularly the work in and near Moll’s group, that helped to establish the basis for today’s electronics. The Si diffused‐impurity devices of 1954–55 are described, including work and data not previously reported or broadly known—in fact, much work and data (a new technology) that was carried across the Country to a place that became known as Silicon Valley. For further perspective, an appendix is included of independent early suggestions of Bardeen (Urbana notebook, Feb 1952) to leave Ge in favor of diffused Si devices. © 2003 American Institute of Physics

ISSN:0094-243X    

DOI:10.1063/1.1622452

出版商:AIP    

年代:1903

数据来源: AIP

摘要:

The phenomenal growth of the semiconductor industry has been made possible by our ability to deliver more functionality at a lower and lower cost, with a reduction in cost per function of approximately 25&percent; per year. Technology advancements have also enabled higher performance, lower operating voltages, and associated lower power consumption. Dimensional shrinks based on 248 nm lithography led the revolution in recent years. However, with the fundamental limit for optical lithography at about 1/3rdthe wavelength, the limits for 193 nm and 157 nm lithography are about 65 nm and 50 nm respectively. With EUV and most other NGL technologies 7 years in the future the limit for the remainder of the decade is about 50 nm. Technology challenges, whether they are lithographic in nature or based on needed new materials with advanced properties, are summarized in this paper along with suggestions for potential solutions for the remainder of the decade. Even if we meet the technology challenges, continued revenue growth and profitability will become more and more challenging. The need for larger and larger technology R&D budgets may make it difficult for the current number of semiconductor manufactures and equipment and materials suppliers to remain profitable. The solution to this conundrum is now clear — partnerships and collaboration. Meeting this challenge of creative cooperation with existing and new partnerships is the new paradigm that is discussed here in some in detail. © 2003 American Institute of Physics

ISSN:0094-243X    

DOI:10.1063/1.1622453

出版商:AIP    

年代:1903

数据来源: AIP

摘要:

Development of CMOS technology is approaching severe technological limits in the next 10 – 15 years. Overcoming these limits will demand introduction of new manufacturable materials and device structures to extend the speed of silicon integrated circuits at the historical rate of 17 &percent; per year to the end of the 2001 International Technology Roadmap for Semiconductors (2016). Following a brief discussion of these limits, this paper will review the most promising approaches to new materials, device structures and issues related to their integration in advanced CMOS \ structures. The paper will conclude with some brief observations and issues regarding extension of CMOS‐like FET structures via new nano‐scale materials. © 2003 American Institute of Physics

ISSN:0094-243X    

DOI:10.1063/1.1622454

出版商:AIP    

年代:1903

数据来源: AIP

摘要:

The semiconductor industry continues to fabricate integrated circuits (ICs) with faster clock speeds, increased numbers of transistors, and smaller feature sizes. A complete set of the attributes describing a new technology generation (or node) is specified by an important features size such as the12pitch of the first level of metal lines in a dynamic random access memory (DRAM). Historically, Moore’s law has been used to describe the timing associated with the three‐year cycle of new generations of memory devices. Recently, the introduction of new generations of logic devices has surpassed the three‐year node cycle of memory devices. New technology generations have another significance. Each generation requires a new set of manufacturing equipment and, recently, new materials. TheInternational Technology Roadmap for Semiconductors(ITRS) describes the technology requirements for volume manufacturing of integrated circuits (ICs) for each new technology node over the next 15 years [1]. In the 15‐year horizon of the current ITRS, industry experts are considering the possibility of a revolution in microelectronics. The ITRS predicts that the gate length of transistors at the end of the roadmap will be less than 10 nm. The ITRS also discusses the need to move beyond traditional planar CMOS during the next 15 years and the potential need to move into revolutionary technologies at the end of the roadmap. The physical properties of materials change from bulk‐like into “nano‐like.” For example, on‐chip interconnects will have dimensions that have nanowire properties. The development and manufacture of new generations of ICs or their successors will require new measurement technology. There will be many different challenges for metrology over the next 15 years. This paper describes these challenges. © 2003 American Institute of Physics

ISSN:0094-243X    

DOI:10.1063/1.1622455

出版商:AIP    

年代:1903

数据来源: AIP

摘要:

The National Institute of Standards and Technology metrology development for the semiconductor industry and its supporting infrastructure is a broad set of programs directed at many of the critical metrology needs. This paper will give examples of specific projects addressing needs in lithography, critical dimension and overlay, gate dielectric characterization, interconnect materials, and manufacturing support. The paper will emphasize the role collaboration with industry plays in project selection, project success, and transfer to industry. © 2003 American Institute of Physics

ISSN:0094-243X    

DOI:10.1063/1.1622456

出版商:AIP    

年代:1903

数据来源: AIP

摘要:

The evolution of planar, conventional CMOS to non‐classical CMOS devices as described in the International Technology Roadmap for Semiconductors (ITRS) is discussed. The benefits of strained silicon configurations to enhance the channel mobility, silicon‐on‐insulator (SOI) to enhance the reduction of residual parasitics and non‐planar transistor device structures to improve control of the short‐channel effects are discussed. The combination of the above enhancements, in conjunction with the current state‐of‐the art global efforts in high‐k gate dielectrics, metal electrodes and elevated source/drain, offers a plethora of opportunities requiring careful assessment of the optimal solution for each organization’s portfolio of products and projected market position. Several of these possible solutions for the “ultimate” CMOS device are discussed from today’s perspective, with attention to the characterization and metrology for assessing these alternate device structures. © 2003 American Institute of Physics

ISSN:0094-243X    

DOI:10.1063/1.1622457

出版商:AIP    

年代:1903

数据来源: AIP

摘要:

We review the characterization of optical properties of high‐K gate dielectric films and film stacks. Modern high‐K dielectrics typically incorporate an ultra‐thin oxide interfacial layer designed preserve the channel mobility. High‐K filmstack physical characterization data is presented and correlated to the optical response of the material determined via spectroscopic ellipsometry. In‐line measurement of film physical thickness relies on the optical models used for fitting the dielectric function. Optimal optical models for use in process control are discussed, as well as limitations of spectroscopic ellipsometry to characterize high‐K dielectric/interfacial oxide stacks. We also discuss the application of spectroscopic ellipsometry to characterize high‐K dielectrics on silicon‐on‐insulator substrates. © 2003 American Institute of Physics

ISSN:0094-243X    

DOI:10.1063/1.1622458

出版商:AIP    

年代:1903

数据来源: AIP

摘要:

Targeting very thin equivalent oxides (<1 nm) requires the deposition of (very) thin dielectrics onto silicon surfaces with minimal interfacial oxide. Typically, high‐k dielectric layers are deposited using ALD or MOCVD with, at present, a prime emphasis on Hf‐based high‐k dielectrics, either as pure HfO2, as silicate, or mixed with Al2O3. Depending on the deposition conditions, serious deficiencies in terms of film closure and material density occur for the ultra thin (<3 nm) films which are required for very small EOT’s. As such, critical metrology needs arise enabling one to study details of the film growth and its evolution upon thermal anneal. As discussed in this paper, many tools are required such as Rutherford Backscattering Spectrometry and high‐resolution elastic recoil detection (ERDA), Low Energy Ion Scattering, Time‐of‐flight SIMS, (spectroscopic) ellipsometry and X‐ray photoelectron spectroscopy. When trying to correlate these different methods one must be aware of potential discrepancies due to non‐homogeneous growth and reduced material density. Local electrical measurements based on tunneling atomic force microscopy reveal very fine scale inhomogeneities, which can be correlated to local structural defects. © 2003 American Institute of Physics

ISSN:0094-243X    

DOI:10.1063/1.1622459

出版商:AIP    

年代:1903

数据来源: AIP

摘要:

We present in this paper the results of advanced characterization, by photoemission using the soft x‐rays of a synchrotron source, of the interface between chemically oxidized Si and 0.6 nm HfO2. The benefits of such a source enables us to determine the chemical nature and estimate the spatial structure of the intermediate layer between the high‐&kgr; material and the Si substrate. It is shown that this layer consists of two sub‐layers, the first being pure SiO2extending over 0.64 nm and the second being Hf‐silicate (HfO2)x(SiO2)1−xwith x=0.44 and a thickness estimated to be 0.22 nm. The present approach should apply to the study of other Si/high‐&kgr; materials interfaces. © 2003 American Institute of Physics

ISSN:0094-243X    

DOI:10.1063/1.1622460

出版商:AIP    

年代:1903

数据来源: AIP