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1. |
A design of automatically tunable active MOSFET‐RC filters using a single‐ended circuit structure |
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Electronics and Communications in Japan (Part III: Fundamental Electronic Science),
Volume 73,
Issue 10,
1990,
Page 1-12
Takahiro Inoue,
Fumio Ueno,
Satoru Sonobe,
Mikio Kawasaki,
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摘要:
AbstractRecently, as a new continuous‐time filter, an automatic tuning MOSFET‐Cfilter was proposed by Banu and Tsividis. It consists of MOSFETs, capacitors and operational amplifiers. It was shown that a highly accurate filter can be realized. In this configuration, only the voltage‐variable MOSFET resistor is used as the resistor and its non‐linearity is eliminated by a circuit configuration such as a fully balanced type.This paper proposes an active MOSFET‐RCfilter in which elimination of the nonlinearity of the MOSFET resistor does not require matching between MOSFETs. The filter consists of MOSFETs, capacitors, linear resistors with identical values and operational amplifiers, and can be made of a single‐ended circuit.An automatic tuning of the filter characteristics is possible via a control of the resistance value of the MOSFET resistor with a PLL made of a voltage‐controlled all‐pass filter. Based on this configuration, a third‐order elliptic low‐pass filter was constructed with discrete components. With a power supply voltage of ±5 V, the filter characteristics were a total harmonic distortion of less than 0.1 percent, a dynamic range of more than 110 dB, and a passband gain variation of less than ±0.1 dB in the temperature range of −20°C to 80°C for a filter input volt
ISSN:1042-0967
DOI:10.1002/ecjc.4430731001
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1990
数据来源: WILEY
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2. |
Functional simulation of color signal processor for VTR by digital dynamics simulation language |
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Electronics and Communications in Japan (Part III: Fundamental Electronic Science),
Volume 73,
Issue 10,
1990,
Page 13-29
Shin‐Ichi Hayashi,
Toshinori Watanabe,
Makoto Furihata,
Norihisa Yamamoto,
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摘要:
AbstractWith the development of semiconductor integration, the technology has arrived at the stage of the system‐on‐chip. With the widespread use of application specific IC (ASIC), the small‐quantity production of diversified types is required. Then it is important to reduce the design period for the mixed analog/digital circuit.VTR color signal processing LSI is a typical mixed analog/digital circuit. It has the scale of 500 analog elements and 800 digital elements, and it is too time‐comsuming to simulate the operation of the whole LSI by the conventional circuit simulator. Thus, a functional simulator is required for the large‐scale mixed analog/digital LSI.This paper proposes a functional simulation, employing techniques of continuous system simulation. The technique is applied to the design of a mixed analog/digital circuit, where the conventional method has been unsatisfactory, and the method is shown to be useful in the Functional design of the circuit. The method is based on the modeling of the mixed analog function/circuit, and can be applied to the VTR color signal processing LSI.The functional simulation can easily be performed with the complete knowledge of the analog function. Consequently, the method can contribute greatly to the quality improvement of the design and the reduction of the desi
ISSN:1042-0967
DOI:10.1002/ecjc.4430731002
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1990
数据来源: WILEY
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3. |
Relationship between acceleration factor of weibull‐type lifetime distribution and proportional hazard model |
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Electronics and Communications in Japan (Part III: Fundamental Electronic Science),
Volume 73,
Issue 10,
1990,
Page 30-35
Hiroshi Shiomi,
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摘要:
AbstractBased on the knowledge concerning the life test for Weibull distribution, this paper considers the regression model for the reliability proposed by Cox et al., especially the proportional hazard model assuming Weibull distribution. Also discussed are the properties of the functiongterm representing the effect of factorxother than timet.First, the relation between the regression expression for thegterm and the reaction rate model is presented. It is shown that thegterm corresponds to the failure rate acceleration factor in the accelerated life test, and is related directly to the lifetime acceleration factor as well as other acceleration factors for the reliability parameters.An analogy is made between the expression that the reliability at the reference state to the power ofgis equal to the reliability in the accelerated state, and the weakest link model forglinks. Based on that analogy, it is shown that the reliability in the accelerated state is equivalent to the reliability of the series structure ofgindependent components with the reliability at the reference state. Thus,gcan be integrated as an acceleration factor representing a kind of scaling effect. It is shown also thatgcan be considered in the high‐reliability range as a reduction factor for the number of samples required to ensure reliabilit
ISSN:1042-0967
DOI:10.1002/ecjc.4430731003
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1990
数据来源: WILEY
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4. |
A design method for coherent optical fiber filters of direct form |
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Electronics and Communications in Japan (Part III: Fundamental Electronic Science),
Volume 73,
Issue 10,
1990,
Page 36-45
Chae‐Wook Lee,
Kohichi Sakaniwa,
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摘要:
AbstractRecently, optical signal processing has attracted considerable attention for highspeed and broadband signal processing such as channel separation filtering for optical FDM signals.This paper considers coherent optical fiber filters which use coherent light sources and consist of directional couplers and optical fiber delay elements. These optical fiber filters are permitted to have both positive and negative value for filter coefficients, but still differ from the usual digital filters, since in the optical fiber filters, (1) the coupling coefficientaof a directional coupler is restricted to the value between 0 and 1, (2) optical signalE(complex amplitude) is divided intoj√a Eand √1‐aEat the directional coupler, and (3) for input signalE1andE2, the output of a directional coupler is given by √1‐aE1+j√a E2.Considering these restrictions, we clarify the realizability condition and establish the optimal design method for optical fiber filters of direct form which make best use of optical si
ISSN:1042-0967
DOI:10.1002/ecjc.4430731004
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1990
数据来源: WILEY
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5. |
An estimation method of the pairing and ordering for IIR digital filters with low roundoff noise |
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Electronics and Communications in Japan (Part III: Fundamental Electronic Science),
Volume 73,
Issue 10,
1990,
Page 46-60
Yoshinari Oguro,
Toshinori Yoshikawa,
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摘要:
AbstractThis paper considers the IIR cascade digital filter based on the fixed‐point arithmetic, and presents a method for estimation of the optimal pairing and ordering to minimize the output roundoff noise. In the proposed method, the computational complexity required in the estimation is reduced by considering only the pole frequencies of the transfer function in the evaluation. In the scaling of each branch node, the generalL2‐ andL∞‐norms are assumed.The proposed method is compared with the methods of Jackson, Lee and Liu‐Peled which are used frequently in practice. The four methods are applied actually to two kinds of filters, and the computational complexities are compared. It is shown as a result that the proposed method requires almost the same computational complexity as those of Jackson and Lee from the lower‐order to higher‐order filters, and realizes the pairing and ordering with smaller output roundoff noise. It is shown also in general that the pairing has a larger effect on the normalized output roundoff noise than
ISSN:1042-0967
DOI:10.1002/ecjc.4430731005
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1990
数据来源: WILEY
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6. |
Improvement of linearity in switched resistors |
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Electronics and Communications in Japan (Part III: Fundamental Electronic Science),
Volume 73,
Issue 10,
1990,
Page 61-68
Sumio Fukai,
Hirobumi Ishikawa,
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摘要:
AbstractSwitched resistor circuits have been proposed as a realization of equivalent resistors suitable for monolithic integrations. Since the linear resistance region of an MOSFET has been used, the dynamic range of the signal handled has been small. This paper presents methods for improving the linearity of the MOSFET suitable for a switched resistor circuit. With a view to configurations with fewer circuit elements, a method is considered for feedback from the drain to the gate and a method in which the nonlinearity is cancelled with two matched MOSFETs. It is confirmed experimentally that a practical dynamic range can be obtained and a high resistance can easily be realized with these methods for improvement.
ISSN:1042-0967
DOI:10.1002/ecjc.4430731006
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1990
数据来源: WILEY
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7. |
Mixed D‐A circuit simulation by one‐way subcircuit time‐first analysis approach |
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Electronics and Communications in Japan (Part III: Fundamental Electronic Science),
Volume 73,
Issue 10,
1990,
Page 69-79
Tetsuro Kage,
Shintaro Shimogori,
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摘要:
AbstractThis paper considers the mixed digital‐analog (D‐A) circuit which contains both logic gates and analog elements such as bipolar transistors. A mixed D‐A circuit simulator was developed which directly simulates the mixed D‐A circuit. The simulator combines closely the logic simulation and circuit analysis, and provides an accurate and efficient simulation of the mixed D‐A circuit. The management of the simulation time is different for the logic simulation and the circuit analysis. By simply combining those two techniques, it is difficult to provide an efficient simulation for the general mixed D‐A circuit containing a feedback loop.From such a viewpoint, a simulation method was developed in which the mixed D‐A circuit is decomposed into blocks along the direction of the signal propagation, and each block is simulated by time‐first processing. The block containing a mixed D‐A loop is decomposed hierarchically into blocks until the analog subcircuit is separated. By the proposed method of simulation, an efficient simulation is provided for the general mixed D‐A circuit containing a feedback loop by grouping the processing for the analog subcircuit. However, thi
ISSN:1042-0967
DOI:10.1002/ecjc.4430731007
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1990
数据来源: WILEY
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8. |
RSA security |
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Electronics and Communications in Japan (Part III: Fundamental Electronic Science),
Volume 73,
Issue 10,
1990,
Page 80-88
Kaoru Kurosawa,
Kazuo Matsu,
Hirohumi Kasai,
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摘要:
AbstractRSA is a typical public key cryptosystem, but whether or not breaking RSA is as hard as prime factorization is unknown. It is known that if the LSB sequence obtained from iterated cipher texts of RSA is distinguished from the true random sequence in a polynomial time, it is possible to break RSA. Consequently, by testing the quality of this pseudorandom sequence, the security of RSA can be evaluated. It is known also for RSA that guessing the least‐significant bit of the original message from the encrypted message with probability 1/2 + 1/poly(n) is equivalent to finding the whole original message.In this paper, it is shown first that guessing the value of the original message by modLwith probability 1/L+ 1/poly(n) is as difficult as finding the entire original message. Based on the result, a multivalued pseudorandom number generator is given. Those based on the hardness of the quadratic residue property also are shown. Statistical testing of those pseudorandom numbers is attempted, leading to the evaluation of the reliability of RS
ISSN:1042-0967
DOI:10.1002/ecjc.4430731008
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1990
数据来源: WILEY
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9. |
A global router for standard cell VLSI with feed‐through assignment optimization |
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Electronics and Communications in Japan (Part III: Fundamental Electronic Science),
Volume 73,
Issue 10,
1990,
Page 89-101
Yasuo Sugai,
Hironori Hirata,
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摘要:
AbstractA global routing for a standard cell VLSI poses two important problems: how often we use it with feed‐through and where to install it beside the layout to trunk lines. To minimize the total number of tracks at the level of detailed routings, we avoid local congestions. Thus the layout touting with feed‐through becomes necessary which does not depend on the routing order. For an optimization problem for a large number of combinations of routings, Kirkpatrick et al. have proposed a simulated annealing method. This method is a stochastic sequential improvement method. Its features are an ability to escape from local solutions and the obtained solution depends on the initial conditions and routing order. In this paper we proposed a new method for a global routing for a three‐layer standard cell VLSI with feed‐through based on the simulated annealing method. Features of our method are an enhanced degree of freedom of routings, allowance for changes of directions of feed‐through and an effective acoidance of local congestions. Through experiments on a computer we achieved a drastic reduction of the number of tracks compared with that of the existi
ISSN:1042-0967
DOI:10.1002/ecjc.4430731009
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1990
数据来源: WILEY
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10. |
Culation algorithms of primary functions on a digital signal processor |
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Electronics and Communications in Japan (Part III: Fundamental Electronic Science),
Volume 73,
Issue 10,
1990,
Page 102-110
Tsuyoshi Ebina,
Rokuya Ishii,
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摘要:
AbstractRecently, many kinds of digital signal processing systems are proposed. In realizing these systems on a digital signal processor (abbreviated as DSP), in most cases primary functions must be computed. When we compute primary functions on DSP, we make tables and use them for these function values for requirements. By using this method, we cannot obtain precise values and thus require a large memory region for tables. If we use DSP for complicated computations, application fields are limited.This paper presented calculation methods of a division, sin(X), cos(X), tan(X), an arctangent, a square root, a logarithm and an exponential function. Further, execution speeds and execution precision were obtained. We used the digital signal processor MSM6992 made by OKI Electronic Industry Co. On the DSP, the execution program step number is 24 to 77.The calculation error is less value than 2 to 4 times the value which corresponds to the least significant bit in a DSP with floating point arithmetic. Calculation of primary functions by the proposed methods does not require a large memory region (except for the calculation of a square root of an exponent). Then using proposed methods, we can implement a complex system using primary functions on a one‐chip DS
ISSN:1042-0967
DOI:10.1002/ecjc.4430731010
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1990
数据来源: WILEY
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