摘要:

AbstractIt is often pointed out that existing object‐oriented analysis/design methods have problems that make comprehension of design diagrams difficult because too many classes are displayed in a single diagram, design diagrams cannot be reused and details of dynamic behavior cannot be described on design diagrams, etc. To solve these problems, an object modeling method called SOMM is proposed and its modeling environment SOME is proposed where design diagrams are hierarchically structured.With SOMM, objects are modeled from different viewpoints and are represented using four types of diagrams. Derivation Diagram: DD expresses inheritance relationships among classes; Object Diagram: OD represents association among classes; Even‐trace Diagram: ETD shows even communication sequence among classes; and State‐transition Diagram: STD expresses state transitions in a class life cycle. Aggregation among classes is represented by embedding (Zoom In) an object diagram into a class of another object diagram. As a result, the diagrams are hierarchically structurized. Moreover, because the diagrams are made and controlled for each class, reuse is easy.Further, all these three models of a class are stored in an integrated object, so SOME can check inconsistency among related diagrams and correct them.Meanwhile, the event‐trace diagram is extended to represent the details of dynamic behavior of a class, especially the sequence of reactions to the incoming event. Thus the programs could be made systematically and directly from the d

ISSN:0882-1666    

DOI:10.1002/scj.4690271101

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractWired‐logic is especially useful when designing fan‐in restricted logic circuits which are implemented with bipolar and MOS transistors. There is, however, little published on the subject outside of the work done by the present authors. In this paper, a method of reducing the levels of circuits by utilizing Wired‐Logic is presented. The method restricts the number of fanins for a gate utilizing Wired‐Logic and transforms circuits using the transduction method optimization. To attain the proper combination of NOR gates and Wired‐OR gates, an algorithm using Wired‐OR gates for the fan‐in restriction is also presented. By performing experiments on third level NOR circuits, the proposed method is comparable toGeneralized Serial Duplicationwhich is an efficientserial duplication.The levels of most circuits are reduced by Wired‐OR gates, thereby demonstrating the efficiency of Wired‐Logic. Although connection length is important to LSI, the cost function simplifies circuit levels. Hence, for the purposes of this paper, analysis is expanded to include

ISSN:0882-1666    

DOI:10.1002/scj.4690271102

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractThis paper discusses a schema integration and query processing method that enables integrated access to the multiple autonomous databases in the distributed environment with schemata restricted to a set of attributes. This method is based on the construction of a virtual database (VDB) formed over physically distributed component databases. Although user queries are issued to this VDB, these queries are decomposed to the subqueries using the virtual functional dependency (VFD), which is defined on the VDB and issued to each actual component database. The VDB‐based method can obtain more answers that are logically valid than those gained from conventional query processing methods. When the VFD formed over a VDB is acyclic among the nodes to which the query refers, sound and complete answers can be efficiently calculate

ISSN:0882-1666    

DOI:10.1002/scj.4690271103

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractConsideration is given to predicting the realizability of the logic synthesis and the circuit scale after the logic synthesis at the stage of the functional design before the logic synthesis. If this is realized, the manual re‐design part, as well as the execution time for logic synthesis can greatly be reduced, which is a problem at the present logic synthesis.This paper considers the stage of HDL description (functional description) at the register transfer level (RTL) before the logic synthesis based on the hardware description language (HDL). It presents a method of synthesis prediction, which can predict the realizability of the logic circuit expected after the logic synthesis. In the proposed synthesis prediction, the expertise of the HDL description for the logic synthesis integrated into the knowledge in the database and the following functions are provided.The synthesis possibility function determines the realizability of the logic synthesis using the constructed synthesis template. The guidance function transforms interactively the HDL description, for which the logic synthesis is decided as unrealizable, into the logic synthesis description for which the logic synthesis is possible. The predictive estimation function estimates the circuit scale (in terms of the number of logic gates) after the logic synthesis.The proposed synthesis prediction methodology is applied to the HDL macrogeneration system. It is seen that the logic circuit as intended by the designer is obtained by the logic synthesis, and the predicted number of logic gates agreed with that of the circuit after the logic synthesis within ± 10 percent, in terms of the median value. The proposed synthesis prediction can be executed with more than 100 times higher speed compared to the actual logic synthesis execution ti

ISSN:0882-1666    

DOI:10.1002/scj.4690271104

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractOne of the important issues in the asynchronous sequential circuit is to verify that the state transitions as stated in the specification occur even if there is a delay variation in the element. When the exiting timing verification method is applied to this problem, however, the transient and other states must be examined, which requires an exponentially long time in the verification. This paper presents a formal procedure based on the circuit structure and the relation between the specification and the circuit, where the state transition to induce the transition in the specification is determined and the state transition to be verified in detail is restricted without generating the transient and other states.First, the time‐invariant input values and state variable values are considered, and a sufficient condition is given for the above restriction. The sufficient condition ensures that the state transition occurs as is stated in the specification, independently of the element delay. A decision procedure for the sufficient condition is presented, and the time complexity is examined. It is shown that the proposed method is useful in reducing the verification time compared to the existing verification method. The sufficient condition is applied to sample circuits, and it is shown that the detailed verification can be omitted by the factor of 16/17 for the ring arbiter, and 20,24 for the D flip‐flop. Thus, it is expected that the time for the verification can be reduced greatly by the proposed met

ISSN:0882-1666    

DOI:10.1002/scj.4690271105

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractThis paper investigates the influence of noises added to hidden units of multilayer perceptrons. It is shown that a skeletal structure of the network emerges when independent Gaussian noises are added to inputs of hidden units during the error back‐propagation learning. By analyzing the average behavior of the backp‐ropagation learning to such noises, it is shown that the weights from hidden units to output units tend to be small and outputs of hidden units tend to be 0 or 1. This means that the network is automatically structurized by adding the noises. As the result, it is expected that the generalization ability of the network is improved. This network structurization was confirmed by experiments of pattern classification and logic Boolean function learn

ISSN:0882-1666    

DOI:10.1002/scj.4690271106

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractThe authors have developed a submicron‐level defect detection method that avoids the unnecessary detection of grains produced by some layers. As part of an automated visual inspection system for Large‐Scale Integration wafer multilayer patterns, the developed method can detect defects reliably by automatically generating an optimum threshold for each pattern according to the occurrence of grains in each area of the pattern, and then binarizing the subtracted grayscale images with the threshold. This method is used in comparison inspections of periodic cell patterns in the same die. This can be realized without using design pattern and process information. This paper proposes an edge‐preserving grain‐noise smoothing algorithm that generates a uniform threshold for each region surrounded by the pattern edges according to the grains detected using the multiple cell patterns to be inspected. It is confirmed through experiments with actual LSI wafers that defects on the order of 0.5 μm and greater, which exist at pattern edges and in the regions having no grains, can be detected stably without the unnecessary detection of grains, even with grain sizes on the order of 1 ∼ 1.3 μm in

ISSN:0882-1666    

DOI:10.1002/scj.4690271107

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractThis paper proposes processible video codec on camera operations (PVCC) which uses two video data (camera parameters and image contents) to improve the efficiency of video editing. Image data are separated in the coding; they are selected and synthesized in the decoding. Conditions are set for the relationship between the positions of a camera and its object so that data separation is simplified in the decoding. The system using test patterns shows that the system has an average SNR of about 50 [dB] with accurate camera parameters, the value being sharply deteriorated with an increase of errors in the parameters. Simulations of camera operation and data editing successfully confirm the expected effect of the proposed method. A simple language describing the camera improves the speed of video editing and increases content readability.

ISSN:0882-1666    

DOI:10.1002/scj.4690271108

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractThis paper proposes the Recurrent SOLAR (Supervised One‐shot Learning Algorithm for Real number inputs) algorithm, that can complete learning by a single presentation of analog time series data. The most remarkable feature of the Recurrent SOLAR is the one‐shot learning, which has been difficult in the past modes, and which can be completed with a high speed by a single presentation of the time‐series input data composed of real numbers. The basic idea of the Recurrent SOLAR is the same as in the context model. The time is considered as discrete, and the connection weight of the feedback loop from the output unit or the hidden unit to the state units is fixed. Consequently, the recurrent network can be considered as a feed‐forward network.The backpropagation algorithm is used in the context model, while the SOLAR algorithm is applied to the Recurrent SOLAR, which is the one‐shot learning algorithm based on the pattern recognition theory. By the use of the SOLAR algorithm, the Recurrent SOLAR can learn the analog time‐series data by a single presentation without falling in a local minimum even for large‐scale data. In other words, it is a learning algorithm that is suited to an environment where high speed is required in

ISSN:0882-1666    

DOI:10.1002/scj.4690271109

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY