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1. |
Node processor for a parallel object‐oriented total architecture A‐NET |
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Systems and Computers in Japan,
Volume 27,
Issue 10,
1996,
Page 1-13
Tsutomu Yoshinaga,
Takanobu Baba,
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摘要:
AbstractA node processor for a highly parallel computer based on a parallel object‐oriented computational model has been developed. The node processor consists of a PE for the execution of methods and a router for the control of message communication. The prototype PE has a high‐level instruction set that includes message sending and receiving instructions. It also supports both tagged data structure as a synchronization mechanism and dynamic data typing. The special hardware unit for tag processing achieves a speed up of about 44 percent for an add instruction.The router has been designed as independent to network‐topology. It takes approximately 5.2 μs to transfer a 35‐byte message to an adjacent node. Message transfers over multiple nodes take approximately 1.0 μ
ISSN:0882-1666
DOI:10.1002/scj.4690271001
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1996
数据来源: WILEY
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2. |
A parsing method for context‐free languages using bottom‐up lookahead computation |
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Systems and Computers in Japan,
Volume 27,
Issue 10,
1996,
Page 14-22
Yoshimichi Watanabe,
Takehiro Tokuda,
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摘要:
AbstractA new parsing algorithm of context‐free languages using bottom‐up computation of lookahead information is presented. Earley's algorithm uses a great number of items during enumeration to recognize a context‐free language. If items with lookahead fields are used, the number of items can be reduced, but item spacing is considerably increased. The method presented here may reduce the number of items during enumeration without using lookahead fields of items. The computation of lookahead information takes place in a bottom‐up manner. It is not necessary to compute lookahead information until it is required during enum
ISSN:0882-1666
DOI:10.1002/scj.4690271002
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1996
数据来源: WILEY
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3. |
A method of shortening metastable operation duration time by the use of feedback |
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Systems and Computers in Japan,
Volume 27,
Issue 10,
1996,
Page 23-32
Yoichiro Sato,
Takuji Okamoto,
Yuji Sugiyama,
Masahiro Kawai,
Toshifumi Kobayashi,
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摘要:
AbstractIf metastable operation (MS operation) occurs in conflict‐resolving circuits, propagation delay time of flip‐flop (FF) increases by the amount of its duration time and a malfunction may occur. This paper proposes a method of shortening duration time of MS operation that occurs when two inputs of RSFF consisting of CMOS NAND gates are switched from logic 0 to 1 approximately at the same instant. The MS operation is detected and fed back to inputs so that it is forced to terminate. A configuration of RSFF that has feedback based on this idea is first presented, and then a principle of shortening MS operation duration time follows. Then, considering implementation of RSFF by n‐well process, feedback connection and MOSFET parameters are optimized. Although hardware increases slightly by addition of feedback, the result shows the MS operation duration time increase rate against input phase difference (switching time difference of two inputs of RSFF), and the range of input phase difference for MS operation incidence are reduced by approximately 1/4 and 1/3, respectively, compared with conventional me
ISSN:0882-1666
DOI:10.1002/scj.4690271003
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1996
数据来源: WILEY
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4. |
A phase connection method for communication protocols |
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Systems and Computers in Japan,
Volume 27,
Issue 10,
1996,
Page 33-47
Tetsuo Sano,
Masahiro Higuchi,
Hiroyuki Seki,
Tadao Kasami,
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摘要:
AbstractAs one of the methods to define a large‐scale protocol by combining multiple subprotocols, Chow et al. proposed a method in which protocols satisfying a certain condition called phase are serially connected. In their method of connection, however, two conditions for connection are imposed: 1) the protocol machine should be modeled as a finite‐state machine; and 2) the two‐way channels should both be empty at the termination of the phase.This paper relaxes those two constraints, and proposes a more general method of phase connection. Using the method proposed in this paper, it is made possible, for example, to define the protocol containing the token passing control by connecting two phases, where the token is fixed in one of the protocol mac
ISSN:0882-1666
DOI:10.1002/scj.4690271004
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1996
数据来源: WILEY
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5. |
Realization of multiwindow system with high‐speed operations of nonrectangular windows |
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Systems and Computers in Japan,
Volume 27,
Issue 10,
1996,
Page 48-58
Toshiyuki Maeda,
Yoichiro Sato,
Tokumi Yokohira,
Takuji Okamoto,
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摘要:
AbstractThis paper describes the realization of the multi‐window system, where the framed nonrectangular windows can be operated with a high speed. The body image (the image to be displayed inside the frame) and the frame image (the image to be displayed as the frame), which are stored on the multiport memory, are read out in parallel, being synchronized to the CRT scanning. By selecting pixelwise one of those images, the window image displayed in the window is generated as a framed image. The selection signal for this purpose is generated based on the window shape information stored in the dedicated memory.The multiwindow image is generated by selecting the image to be displayed for each pixel position on CRT using a hardware. A distributed priority encoder is used as the hardware for this purpose. According to the result of construction and experiment, it is expected that the multiwindow system can realize a sufficiently high‐speed operation from the practical viewpoint for the 1200 × 1000 CRT screen using the existing circuit techno
ISSN:0882-1666
DOI:10.1002/scj.4690271005
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1996
数据来源: WILEY
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6. |
Error description on algebraic specification and its automatic addition |
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Systems and Computers in Japan,
Volume 27,
Issue 10,
1996,
Page 59-67
Takeshi Hamaguchi,
Shinichirou Yamamoto,
Kiyshi Agusa,
Masahiko Sakai,
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摘要:
AbstractWe define an algebraic specification having a framework for error handling and give an algorithm for automatically appending error description. Generally, error description in algebraic specification is so complicated that it is difficult to comprehend and inconsistencies arise if handwritten. Therefore, it is effective to add error description automatically to algebraic specification that has no error description and without creating any inconsistency. Error constructors are introduced that represent error values as a framework for error handling. When there exists a term which is not equal to any constructor term, an equation to equalize the term and an error constructor are appended. To avoid inconsistency, i.e., normal value and error value become equal, we distinguish three kinds of variables. Some variables can be substituted for only by normal terms, some variables can be replaced only by error terms and some variables can be replaced by any term. Moreover, we show correctness of automatic error description addition; i.e., partitioning of terms in the normal part of sort is preserved before and after error description addition.
ISSN:0882-1666
DOI:10.1002/scj.4690271006
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1996
数据来源: WILEY
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7. |
StGA: An application of a genetic algorithm to stochastic learning automata |
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Systems and Computers in Japan,
Volume 27,
Issue 10,
1996,
Page 68-78
Masaharu Munetomi,
Yoshiaki Takai,
Yoshiharu Sato,
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摘要:
AbstractReinforcement learning algorithms such as stochastic learning automata are used to increase the probability that an action will succeed in a stochastic environment. Stochastic learning automata generally have the property of extremely slow convergence when they have a large number of feasible actions. This paper presents a novel reinforcement learning algorithm that employs a genetic algorithm to accelerate convergence. This learning algorithm, called a stochastic genetic algorithm (StGA) samples a small number of actions among all feasible ones. Procedures of stochastic learning automata and genetic operations are applied to a set of sampled actions in order to search effectively a feasible space of actions and find the best ones. Through theoretical investigations, a proof is given on convergence of the StGA by using an ε‐optimality of the stochastic learning automata. Moreover, empirical simulations demonstrate the effectiveness of the StGA when there is a large space of feasible actio
ISSN:0882-1666
DOI:10.1002/scj.4690271007
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1996
数据来源: WILEY
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8. |
A construction of back‐propagation neural networks including time delay elements (BPD) |
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Systems and Computers in Japan,
Volume 27,
Issue 10,
1996,
Page 79-88
Masaaki Nishi,
Junji Furuya,
Tadao Nakamura,
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摘要:
AbstractWe propose here a back‐propagation neural network with built‐in time delay elements (back‐propagation neural networks including time delay elements: BPD) where the delay elements are connected so that an output is self‐fedback per neuron constituting the neural network. The learning algorithm for the BPD can be obtained by the most gradient descent method. The processing methods are classified into four types according to the degree of simplification in the course of formulation and whether or not the numerical calculation using the perturbation is introduced in obtaining a differential value. As applied problems, four types of problems are formed based on the combinations in which the input‐output signals of the neural network are analog signals or digital signals. For these four types of problems, the BPD is computer‐simulated by utilizing the four types of processing methods. In addition, which processing method is preferable is examined with respect to the learning processing results and processing time. It will be confirmed that in the BPD a sufficient learning processing effect can be obtained by utilizing a method where a secondary effect is ignored and the formulation is simplified. Moreover, SCNN, Jordan's and Elman's networks are taken as examples of the conventional recurrent neural networks which can handle the time‐sequence problems. Then, the results with the conventional neural networks are compared and examined when adapted to the above‐mentioned four‐type applied problems to confirm the effectiveness of the neural
ISSN:0882-1666
DOI:10.1002/scj.4690271008
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1996
数据来源: WILEY
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9. |
Halftoning technique using genetic algorithms |
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Systems and Computers in Japan,
Volume 27,
Issue 10,
1996,
Page 89-97
Naoki Kobayashi,
Hideo Saito,
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摘要:
AbstractA new halftoning technique using genetic algorithm (GA) has been proposed. GA is the optimal search algorithm based on natural selection. An original gray‐tone image is divided into some equally sized blocks. A binary block of the halftone image is coded as the string in GA. The fitness value for the string is defined according to the visual quality of the halftone image. By using GA, the binary block having the highest fitness value is searched for among every block. The efficacy of the proposed halftoning technique is demonstrated by the results obtained by computer simulatio
ISSN:0882-1666
DOI:10.1002/scj.4690271009
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1996
数据来源: WILEY
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10. |
A consistency verification method for design models in design environments |
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Systems and Computers in Japan,
Volume 27,
Issue 10,
1996,
Page 98-107
Hiroshi Arai,
Yoshiaki Fukazawa,
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摘要:
AbstractThis paper considers the set of tools built in the design environment for digital hardware, and proposes a method to verify the consistency between the set of tools and the data model. In the design support environment which integrates the set of tools with different data models in general, the interchangeability of the design data is maintained through the common data format. In practice, however, semantic gaps are often produced between the data models.In the proposed method, the data models of the tools and the data models to be presented by the whole environment to the hardware designer are formally defined using the semantic network. The difference between the data models is extracted by operations between the semantic networks. The method was applied to the design support environment based mostly on the netlist information, and the inconsistencies at the semantic level were detected, which has been difficult at the syntax level.
ISSN:0882-1666
DOI:10.1002/scj.4690271010
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1996
数据来源: WILEY
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