摘要:

AbstractA hardware algorithm for computing sine and cosine using redundant binary representation for internal computations is proposed. This paper considers the computation of sine and cosine of angle tH (0; 4) (rad). Our hardware algorithm is a modification of the CORDIC method, and considers gradual rotation of a point on plane orthogonal coordinates about the origin. Sinecosine are calculated by iteratively computing coordinates of the point. The sequences of numbers representingX‐ andY‐coordinates of the point rotated and the remaining angle of rotation are expressed by a redundant binary representation, where each digit of number is an element of {‐1, 0, 1}. The direction of rotation at each step is determined based on the upper 3 digits of the remaining angle, and all the internal computations are done in the redundant binary number system. Since parallel addition and subtraction of two numbers by a combinational circuit can be done in a fixed time regardless of the number of digits in the redundant binary number system, the computation for one step can be done in a fixed time. Following this algorithm,n‐bit computation of sine‐cosine by a combinational circuit can be done in the computation time proportional tonand with the number of elements proportional ton2. Since the computation time proportional to at leastnlognis required in the existing hardware algorithm based on the CORDIC method, our algorithm is more advantageous as the bit length increases. Moreover, faster computation can be done with about the same number of elements for practical bi

ISSN:0882-1666    

DOI:10.1002/scj.4690180801

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1987

数据来源: WILEY

摘要:

AbstractThis paper presents an efficient data management technique for the highly parallel reference engine PIE. PIE aims at the general‐purpose machine in the future knowledge processing. It is a machine which executes logic programming languages with a high speed in OR‐parallel, according to the goal‐rewriting model. In the implementation scheme considered by the authors for the goal‐rewriting model, the initial scheme is the one where the elementary processing unit is generated by a complete copy, and the sharing mechanisms are gradually adopted. The structure data sharing scheme proposed in this paper is a scheme, where the elementary processing units share only the ground instances among the structure data owned by the elementary processing units. In this paper, the structure data sharing scheme is estimated by the software simulations indicating its usefulness. The proposed scheme can reduce the degeneration time and the transfer time of the basic processing units, and improve the processing speed. On the other hand, there appears the overhead due to the lazy fetch, separating and storing of group instances, and garbage collection is required. From the detailed simulation for those aspects, we make a quantitative dis

ISSN:0882-1666    

DOI:10.1002/scj.4690180802

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1987

数据来源: WILEY

摘要:

AbstractThe alternate‐data‐retry (ADR) is a scheme which performs the retry using the 1′s complement of the input data, when an error is detected at the output, etc., of the logic circuit. By applying the scheme to the data‐bus and memory unit where the data are processed without modification, all single stuck‐at‐faults can be masked without considerably increasing the hardware complexity. ADR is also known to be useful for the circuit realizing the self‐dual function, such as adder, even though the data are modified. In the circuit realizing the self‐dual function, however, there may be produced a fault which is not masked by ADR, if the circuit contains a gate with two or more fan‐outs. This paper clarifies the necessary and sufficient condition for such a fault to exist. Based on the result, a circuit construction is proposed in which all single stuck‐at‐faults in the circuit can be masked by ADR, when any logical function is realized as a combinational circuit. By extending the method, a construction of the combinational circuit is shown, in which the double stuck‐at‐fault can also be masked, by employ

ISSN:0882-1666    

DOI:10.1002/scj.4690180803

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1987

数据来源: WILEY

摘要:

AbstractThe mechanism of the lymph flow is not fully understood. Since the lymphatic system has no pump apparatus such as a heart in the blood vessel system, it is important to study the relationship between the lymph flow and the contractile movement of its wall. This paper analyzes the rhythmical contraction of the lymphatics of the rat mesenteryin vivo. Only the image of the lymph vessel wall was extracted from the microscopic image of the mesentery recorded on video tape. An algorithm was developed which was suited to the continuous measurement of the vessel diameter. In the process of the automatic extraction of the lymph vessel wall, not only its derivative and the direction, but also the running state of the lymph vessel were utilized as information. A circular scanning was employed for the first time as a method which realized an accurate diameter measurement of the vessel that always changed its shape with time. By the proposed image processing system, the periodic movement of the lymph vessel could be analyzed quantitatively.

ISSN:0882-1666    

DOI:10.1002/scj.4690180804

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1987

数据来源: WILEY

摘要:

AbstractA key to speeding up the processing is how to realize the programmable hardware using both a pipelined processing scheme and a multiprocessor processing scheme for such special hardware as the fast Fourier transform (FFT) unit and the digital filter. This paper proposes a structure for the programmable logic unit (PLU) based on such an idea, where the computing program is mapped on the hardware, and the processing is performed by write/read of the operand data. For the computer using the proposed PLU, three kinds of conceivable processing algorithms are presented. On the other hand, considering the number of pins, the regularity of the circuits, and the recent progress in three‐dimensional VLSI technology, it is highly conceivable that the proposed PLU is realized by VLSI. Thus, from the viewpoint of program execution in the computer using PLU, the program is constructed of the instructions computed by the PLU and the control instructions executed by the main CPU, and the processing mechanism is described using a program example. A discussion is made on the processing time, and it is shown that the computer using the PLU can utilize the parallelism of the computation by PLU to reduce the processing time, compared with the computer not using PLU. Thus, the effectiveness of the computer using PLU is demonstrate

ISSN:0882-1666    

DOI:10.1002/scj.4690180805

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1987

数据来源: WILEY

摘要:

AbstractThe programmable logic unit (PLU) has been proposed to realize a high‐speed operation. The idea is to perform computation obtained by a static data flow scheme using the stepwise arithmetic logics distributed in the memory. This paper describes the configuration of the prototype PLU, the basic concepts of the computation and the synchronization between the PLU and the main control unit (CU). Then theoretical discussions are made on the computation time for the arithmetic and the iterative programs. It is shown that the high‐speed processing is realized by the effects of the parallel computation and of the pipelined computation, mapping many templates of a loop program on the PLU. Furthermore, the multiprogramming for the computer with PLU is proposed to utilize effectively the waiting time for the computation in the PLU. The throughput improvement is indicated by theoertical analysis, comparing the computer using PLU with the traditional sequential computer. Finally, the usefulness of the PLU is demonstra

ISSN:0882-1666    

DOI:10.1002/scj.4690180806

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1987

数据来源: WILEY

摘要:

AbstractThis paper proposes a highly efficient coding method suited to the storage and transmission of complicated line drawings such as topographical map. Instead of using the method based on the fixed‐length segment such as Freeman's chain code, the segment length is made variable according to the state of the curve. The high efficiency is realized by further adding the directional‐difference code. In the method employing variable‐length segment, there is a danger that the approximate error is increased with the length of the segment. Consequently, a scheme is employed in which the permissible error is specified, and the coding is performed within the error limit. To simplify the encoding procedure, several quantization templates are prepared with different segment lengths, and the approximating segment is selected by taking the template according to the state of the curve. Avoiding the increase of coding complexity by adding the template discrimination code, the template to be used is selected based on the code sequence generated in the past. By this scheme, although depending on the complexity of the line drawing, the coding complexity can be reduced by 25 to 40 percent considering only the effect of variable segment l

ISSN:0882-1666    

DOI:10.1002/scj.4690180807

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1987

数据来源: WILEY

摘要:

AbstractA method of document management in the electronic filing is considered, where the abstract is prepared, filed and retrieved for each document. This paper discusses a method of preparing an abstract from the document image. A method is proposed in which the region marked by the user with a felt‐tip color‐pen, etc., is extracted automatically and filed. The features of the method are as follows: (1) in the extraction of the marked region from the marked document image, the difference of reflectivities between the background (white) and the marked region in the document is utilized; (2) to determine the position of the mark, the algorithm based on the peripheral distribution using the integration of pixels is employed from the viewpoint of speed and accuracy; (3) in the compression to extract only the marked region, a processing to replacen npixels by a pixel is applied, from the viewpoint of hardware implementation and sp

ISSN:0882-1666    

DOI:10.1002/scj.4690180808

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1987

数据来源: WILEY

摘要:

AbstractThe authors have been analyzing images by eye movement. For this purpose, it is necessary to decompose the eye movement into a component to accept information from a gazed object and a component to shift the gazing point. The point considered in the foregoing is called the gazing point, which is defined in this paper based on the property of the pursuit eye movement. Eye movement velocity of 5 deg/s is used as the threshold to separate the two components. As a result, it is made possible to separate clearly the eye movement into the gazing point component and the shift between the gazing point. A vision analyzer based on this definition of the gazing point was developed, which can analyze comprehensively the eye movement in real‐time. As an example of the application of the vision analyzer, the difference of the eye movement in watching the VDT image and the usual dynamic picture is analyzed. Furthermore, as an application to the analysis of art, an experiment was made as a reference material for the analysis of Sharaku's ukiyo‐e painting. The results of experiments are described, indicating that the definition of the gazing point is adequ

ISSN:0882-1666    

DOI:10.1002/scj.4690180809

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1987

数据来源: WILEY

摘要:

AbstractA two‐person perfect‐information game is represented by a minimax game tree and, by solving the tree, we can obtain the result of the game when both players choose perfect moves at all the positions. To this end, various search procedures have been proposed. In this paper, these procedures are modified to implement them on a parallel computer consisting ofmprocessors, and variations of the computation time are investigated withmbeing a parameter. As a theoretical result, we point out that the speedup ratio of the computation time of solving a game tree bymprocessors to that by 1 processor may become larger thanm(acceleration anomaly) or smaller than 1 (detrimental anomaly) in general. Also, we show that the detrimental anomaly does not occur as long as the five search procedures investigated in this paper are used. Next, through simulation experiments, it is shown that the speedup ratio is considerably smaller thanm, and its cause is discussed. The eligible search is considered to be the best among the search procedure investiga

ISSN:0882-1666    

DOI:10.1002/scj.4690180810

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1987

数据来源: WILEY