摘要:

A speech quality almost indistinguishable from human speech has already been demonstrated at the Joint Speech Ressearch Unit (JSRU), using a parallel-formant speech synthesiser. Realisations of this synthesiser have incluede an analogue hardware version, and a simulation as a FORTRAN program. The new sampled-data implementation described here performs the calculations required at a sample rate of 10 kHz on a programmable signal processor chip, the NEC μPD7720. The total synthesiser system, on a small printed circuit, comprises the signal processor chip, three chips for analogue output and filtering, two chips for timing generatation and a four-chip ‘feeder’ computer, which organises the control data into a suitable form. New sets of controls are provided at a 100 Hz rate by some host computer, which organises the control data into a suitable form. New sets of controls are provided at a 100 Hz rate by some host computer, and are interpolated at a 1 kHz rate within the signal processor. The controls are six-bit parameters which specify four formant frequencies, five formant amplitudes, the degree of voicing, the fundamental frequency, and the mark/space ratio of the voiced excitation waveform. For experimental purposes, a control has been added to enable various internal signals in the synthesiser to be observed. The synthesiser has been tested using control signals derived from human speech, but its main application will be with an additional microcomputer to generate speech directly from a linguistic description, by rule.

DOI:10.1049/ip-f-1.1984.0088

出版商:IEE    

年代:1984

数据来源: IET

摘要:

This paper describes the use of a general purpose digital signal processor in the narrowband sections of a satellite receiver. The receiver is an experimental laboratory based tool for investigating the suitability of various demodulation schemes for use with low-cost mobile terminals. To this end six receiver types were implemented, details of three are presented. The architecture of the signal processor used is also described.

DOI:10.1049/ip-f-1.1984.0089

出版商:IEE    

年代:1984

数据来源: IET

摘要:

An important function in underwater passive listening is array processing. Its role is to distinguish, as far as possible, the acoustic targets present in the water. During the last two decades, much effort has been devoted to adaptive array processing to obtain better performance than with conventional beamforming, both in resolving power and protection against high-level sources. However, the amount of computation needed by this processing is great. To reduce the complexity of the processing, new algorithms have been developed. But for important applications, this is still not sufficient. To solve this problem, the processing scheme has been optimised in order to obtain a modular architecture by which systems can be built using the same elementary cascadable processor for many applications. The design of special LSI circuits for adaptive array processing is described and the performance advantages quantified.

DOI:10.1049/ip-f-1.1984.0090

出版商:IEE    

年代:1984

数据来源: IET

摘要:

Current generation sonar acoustic signal processing systems operate at throughputs comparable to those predicted for fifth generation computer systems. Programmable sonar processors are currently deployed that operate with throughputs in excess of 100 million operations per second. These processing speeds are achieved using distributed networks of programmable hardware based primitives which execute the basic signal processing functions. The network of primitives is configured by simple control software to implement the signal processing flow graph that defines the entire sonar processing function.This paper outlines the architecture and development of the processing primitives and their use in high throughput multiprocessor signal processing flow graph systems.

DOI:10.1049/ip-f-1.1984.0091

出版商:IEE    

年代:1984

数据来源: IET

摘要:

Current calculations of optic flow from the motion of edge features in an image sequence are described, and used to illustrate the implementation of low-level image processing calculations on an SIMD (single instruction multiple data) machine. Most of the computational effort in the optic flow calculations is required for carrying out large, multidimensional, spatiotemporal convolutions over the image data, which may be carried out efficiently in parallel by mapping the image pixels into the processor array. Examples are given, showing that computation times consistent with video data input rates can easily be achieved. Later stages of the optic flow calculation, after moving edges features have been detected, are also carried out in parallel, although the computations are no longer completely uniform over the image data arrays. A VLSI processor array, embodying many of the features required for low-level image processing calculations, is briefly described.

DOI:10.1049/ip-f-1.1984.0092

出版商:IEE    

年代:1984

数据来源: IET

摘要:

The advantages of attaining a high computational throughput for numerically intensive digital algorithms through highly parallel distributed processors are described. This approach is shown to be especially appropriate for signal processing rather than more general forms of computing. A machine architecture which exploits this is in course of development and algorithms for real-time processing in radar, speech recognition, image processing and ESM are being developed and benchmarked. The results indicate that the capability of a fully programmable nonspecialised processor of this type compares well with that of contemporary dedicated hardware and promises to exploit small geometry VLSI better than less regular designs of hardware.

DOI:10.1049/ip-f-1.1984.0093

出版商:IEE    

年代:1984

数据来源: IET

摘要:

The transputer and its programming language Occam offer a new approach to digital system design. The transputer is a computer on a chip, which may be used for building highly concurrent systems. Occam is a language in which a system may be described as a set of concurrent processes. Together they can simplify the task of designing and implementing concurrent systems. An ideal application with which to illustrate this is signal processing because it can make simple use of concurrency to build powerful systems. The paper describes Occam and the transputer, and shows how they may be used in a simple signal processing application.

DOI:10.1049/ip-f-1.1984.0094

出版商:IEE    

年代:1984

数据来源: IET

摘要:

The paper discusses progress on the topic of wave filters realised by a variety of approaches in digital technology and presents, in summary, an introduction to relevant theoretical concepts. The implementation of these filters is dependent on the efficient realisation of elements known as adaptors. This paper describes a universal adaptor concept which allows the realisation of either series or parallel adaptors. The Edinburgh FIRST silicon compiler has been used to design the universal adaptor structures, and example circuit layouts are given, in 5 μm NMOS technology, of filters with common frequency-selective characteristics. The future potential of the wave-filter approach to digital filtering is discussed, particularly with reference to CMOS integration.

DOI:10.1049/ip-f-1.1984.0095

出版商:IEE    

年代:1984

数据来源: IET

摘要:

Matrix and vector multiplications are widely used in signal processing in operations such as FIR and IIR filtering, feature extraction and classification. Frequently, signal processing must be done in real time requiring the use of special purpose VLSI hardware. Regular structures such as systolic arrays are well suited for matrix and vector operations and are also amenable to VLSI implementation. This paper describes efficient systolic arrays for matrix and vector multiplication, at both word and bit levels, and outlines three applications relevant for signal processing: a convolver, an IIR filter and a linear classifier.

DOI:10.1049/ip-f-1.1984.0096

出版商:IEE    

年代:1984

数据来源: IET

摘要:

A bit level systolic array for computing the convolution operation is described. The circuit in question is highly regular and ideally suited to VLSI chip design. It is also optimised in the sense that all the cells contribute to the computation on each clock cycle. This makes the array almost four times more efficient than one which was previously described.

DOI:10.1049/ip-f-1.1984.0097

出版商:IEE    

年代:1984

数据来源: IET