摘要:

AbstractTo develop a thermally stable barrier metal for interconnections in LSI, films deposited by sputtering a Ti‐rich TiN0.4target were investigated (in what follows, the film deposited in this manner will be referred to as TiN0.4). Both film quality and the electrical property of the Al‐alloy/Si contact with thin barrier metal were evaluated. It was found that the TiN layer formed by this method was twice as thick as the TiN layer formed by the conventional method, the TiN/TiSi2layer formed was smooth and the silicide layer was five times thinner than when the conventional method was used. The TiN layer formed by nitridation of TiN0.4(50 nm)/Si had a grain structure with a grain size of approximately 10 nm and was strongly oriented to TiN (200). In the silicide layer, the grain size was approximately 50 nm and a semistable phase was formed. It was also found that contact resistance to N+Si was similar to that formed by using the conventional Ti nitridation method while the contact resistance to P+Si was slightly lower than when the conventional method was used. In addition, it was found that the contact resistance became lowest when the rapid thermal nitridation (RTN) temperature was approximately 700°C and the formed film was stable when it was thermally treated. When a Ti layer was used, the N+/P junction showed a leakage problem after it was annealed at temperatures higher than 450°C. However, when TiN0.4was used, no leakage problem was observed even when the junction was annealed at 525 °C. These superior junction characteristics were due to the thermally stable and thick TiN

ISSN:8756-663X    

DOI:10.1002/ecjb.4420790111

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractRecently, with the miniaturization of ULSI patterns, the percentage of the LSI production cost occupied by the multilevel interconnection process is increasing due to the increase in the process steps and the introduction of new materials. In order to realize miniaturization process and achieve cost reduction at the same time, via‐hole maskless multilevel interconnect technology (mask‐less pillar process) has been developed. By merging the via‐hole mask information on the underlying interconnection mask and by a selective etching of the multilevel metal films which depends on the mask width, underlying interconnection and metal pillars are formed simultaneously. The reduction of process steps has become possible by eliminating the via‐hole lithography, etching, and filling process. As a result of electrical measurement of samples formed by the maskless pillar process, the feasibility for two‐level metal interconnection has been verified, which confirmed it to be a multilevel interconnection process suitable for sub‐half micron devices with guaranteed

ISSN:8756-663X    

DOI:10.1002/ecjb.4420790112

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY