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1. |
Study of GaAs FET process using focused ion beam lithography |
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Electronics and Communications in Japan (Part II: Electronics),
Volume 71,
Issue 4,
1988,
Page 1-9
Yoshinobu Sasak,
Hiroaki Morimoto,
Makio Komaru,
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摘要:
AbstractTo construct a highly efficient GaAs FET, it is effective to shorten the gate length. Focused ion beam lithography was utilized to form fine gates. For application of this technique to practical device fabrication, the exposure characteristics of PMMA and the damage to the substrate by the Si‐and Be‐focused ion beams have been investigated. A stable resist profile was obtained with a dose of 2 × 1013ions/cm2. However, the exposure to the ion beams damaged the substrate. To eliminate this damage, a deep recessed structure was adopted and focused ion lithography was used for fabrication of an FET with low noise and medium output power. A gate length of 0.2 to 0.3 μm was realized and an improvement of the device characteristics was demonstrated. As the device structure becomes finer, the gate resistance increases. Therefore, a mushroom gate was formed to decrease the gate resistance. It was shown that focused ion beam lithography is an effective way to form an efficient GaA
ISSN:8756-663X
DOI:10.1002/ecjb.4420710401
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1988
数据来源: WILEY
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2. |
Annealing technology under arsenic overpressure for GaAs LSI–influence on dislocation and threshold voltage |
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Electronics and Communications in Japan (Part II: Electronics),
Volume 71,
Issue 4,
1988,
Page 10-18
Takashi Egawa,
Yoshiaki Sano,
Hiroshi Nakamura,
Katsuzo Kaminishi,
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摘要:
AbstractSince the microscopic uniformity of the threshold voltage (Vth) of an FET is important to obtain GaAs LSI, the cause of the threshold voltage uniformity was researched by investigating the annealing dependencies of the dislocations in the semiinsulating substrate of LEC GaAs and the microscopic uniformity ofVth. Annealing under arsenic overpressure decreased the dislocation density on the substrate surface and formed a uniform distribution of dislocations. This is believed to be caused by the supply of arsenic to the substrate surface. When annealing was carried out under low arsenic pressure,Vthshifted toward the negative direction at the area with clustered pits, and a clear dislocation network was formed. On the other hand, when annealing was carried out under arsenic overpressure using arsene, the shift ofVthin a negative direction becomes small andVthwas distributed uniformly. When annealing was carried out using a protective PCVD SiNxfilm, the distribution ofVthwas consistently uniform, regardless of the dislocation distribution. As described in the preceding, it was found that a high concentration of AsGaexists in the area of the clustered pits, the uniformity ofVthis independent of the dislocation density but dependent on the stoichiometry of the substrate prior to or after annealing, and the distribution ofVthbecomes more uniform with an increase of arsenic concentration.
ISSN:8756-663X
DOI:10.1002/ecjb.4420710402
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1988
数据来源: WILEY
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3. |
Two‐dimensional numerical analysis of gaas MESFET with a p‐buffer layer |
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Electronics and Communications in Japan (Part II: Electronics),
Volume 71,
Issue 4,
1988,
Page 19-25
Nobuko Araki‐Mishima,
Ken Yamaguchi,
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摘要:
AbstractTo suppress the threshold voltage shift of GaAs MESFET's in a shorter channel region, a two‐dimensional numerical analysis of the FET structure with a p‐buffer layer is carried out. As a result of the analysis, it is clarified that the insertion of the p‐buffer layer is effective in preventing the carrier penetration in the substrate. In analyzing the electrical properties as a function of the buffer layer thickness, it is found that the substrate current which flows beneath the p‐channel layer, decreases with an increase in the buffer layer thickness and that the threshold voltage shift is suppressed with the increase. As the buffer layer thickness increases, the transconductance increases. Moreover, as the buffer layer thickness increases, the gate‐substrate capacitance increases. Therefore, to obtain a high cutoff frequency, it is necessary to optimize the buffer layer
ISSN:8756-663X
DOI:10.1002/ecjb.4420710403
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1988
数据来源: WILEY
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4. |
Structure dependence of the short‐channel effect in GaAs MESFETs. Two‐dimensional device simulation |
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Electronics and Communications in Japan (Part II: Electronics),
Volume 71,
Issue 4,
1988,
Page 26-36
Mayumi Hirose,
Yasuo Ikawa,
Nobuyuki Toyoda,
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摘要:
AbstractThe structure dependence of the short‐channel effect in GaAs MESFETs has been investigated using a two‐dimensional device simulator. The short‐channel effect for 1‐μm gate length has been clarified as being due to the decrease in the potential barrier at the substrate region under the channel, especially toward the source. This decrease in the potential barrier increases the current injection into the substrate under the channel, and causes the threshold voltage and a decrease in theKvalue, which is one of the performance criteria of FETs. A structure with a thin source/drain n+layer, an offset structure with a small spacing between the gate electrode and the n+layer, and an LDD structure with an intermediately doped layer between the gate and the n+layer increase the potential barrier effect in the substrate compared to a conventional self‐aligned structure, thereby reducing the short‐channel effect. In addition, the formation of ap‐layer around the n+layer increases further this effect, resulting in an almost short‐channel affect free FET action down to
ISSN:8756-663X
DOI:10.1002/ecjb.4420710404
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1988
数据来源: WILEY
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5. |
A MESFET model for the design of GaAs digital integrated circuits |
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Electronics and Communications in Japan (Part II: Electronics),
Volume 71,
Issue 4,
1988,
Page 37-43
Koutarou Tanaka,
Yasushi Kawakami,
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摘要:
AbstractAs in the case of Si IC's, it is important to carry out circuit simulation in the development of GaAs digital IC's. This paper discusses a GaAs MESFET model for digital IC design. Since in the Shichman‐Hodges model the parameters are obtained only for the saturation region of the drain current, the model is not accurate in the nonsaturation region. Therefore, we utilized additional parameters in the model for the nonsaturation region to increase accuracy. Approximating the potential distribution in an MESFET channel by that in the MOSFET model, the internal capacitance was obtained analytically as a function of the gate and drain voltages. Using the model obtained as described in the foregoing, the transfer characteristic and operational speed of the DCFL circuit were calculated and the results were in excellent agreement with the experimental result
ISSN:8756-663X
DOI:10.1002/ecjb.4420710405
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1988
数据来源: WILEY
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6. |
Study on GaAs monolithic dynamic divider |
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Electronics and Communications in Japan (Part II: Electronics),
Volume 71,
Issue 4,
1988,
Page 44-49
Masafumi Shigaki,
Shigeru Yokogawa,
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摘要:
AbstractThe GaAs monolithic dynamic divider, a high speed divider for microwave phase locked oscillators, has been studied. It can be operated at a higher speed than static dividers. The load in the inverter section is a passive resistor. Improved circuit topology at interstage buffers and reduction of gate resistance by the Au/WSi self‐aligned process have been used for superior characteristics of a single FET. For a 1 μm gate length, both division and frequencies ranging from 4.3 GHz to 7.3 GHz have been observed. As a system application, the divider has been implemented in a 13 GHz frequency synthesizer of oscillator‐multiplier type. The divider has been operated in the 6.5 GHz band and an operation with 1 MHz steps has been confirmed at the 13 GHz band. The phase noise has been 90 dBc/Hz at the off‐carrier frequency of 10 kHz. This value is sufficient for conventional microwave ci
ISSN:8756-663X
DOI:10.1002/ecjb.4420710406
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1988
数据来源: WILEY
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7. |
Transport analysis of a resonant‐tunneling hot electron transistor (RHET) |
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Electronics and Communications in Japan (Part II: Electronics),
Volume 71,
Issue 4,
1988,
Page 50-58
Hiroaki Ohnishi,
Naoki Yokoyama,
Akihiro Shibatomi,
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摘要:
AbstractResonant‐Tunneling Hot Electron Transistors (RHETs) are expected to be an ultra‐high speed and new‐functional device. In this paper the operating principles of RHETs are analyzed and the optimization of the device structure is discussed. For the analysis of the resonant tunneling barrier at the base‐emitter, a self‐consistent method using the Schrödinger and Poisson equations is adopted. To analyze the transport properties of hot electrons in the base, the Monte Carlo method is used. The transfer ratio and device transit time are investigated. Also, a comparison is made between the calculated and measur
ISSN:8756-663X
DOI:10.1002/ecjb.4420710407
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1988
数据来源: WILEY
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8. |
Device analysis of two‐dimensional electron gas (2DEG)FET |
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Electronics and Communications in Japan (Part II: Electronics),
Volume 71,
Issue 4,
1988,
Page 59-71
Toshiyuki Usagawa,
Nobuko Mishima Araki,
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摘要:
AbstractA one‐dimensional analytical model of 2DEG‐FETs has been developed in which the effect of the source‐gate resistanceRsqand velocity saturation are included. When the electron mobility μ, the electron drift peak velocityVe, the source‐gate resistanceRsgand the AlGaAs film thicknessdare varied, the corresponding transconductancegmand the conductance coefficientKare numerically studied in detail. With the present model, the device characteristics of the “MIS”‐like 2DEG‐FET with a thick n+‐GaAs cap layer and an undoped AlGaAs gate have been analyzed. From the point of application of 2DEG‐FETs to a high speed LSI, the design guideline of the device has been studied. For the device parameters of the gate lengthLg= 0.2 μm, the transistor widthW= 10 μm,Rsg= 15 Ω,d= 22 mm, μ = 8000 cm2/Vs andVe= 2 × 107cm/s, the expected device characteristics areK= 10.0 mA/V2, the sourcegate capacitanceCgs= 10.0 fF,gm=
ISSN:8756-663X
DOI:10.1002/ecjb.4420710408
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1988
数据来源: WILEY
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9. |
Systematic design approach for AlGaAs/GaAs HBT using two‐dimensional device simulator and circuit simulator |
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Electronics and Communications in Japan (Part II: Electronics),
Volume 71,
Issue 4,
1988,
Page 72-80
Kazuhiko Honjo,
Mohammad Madihian,
Shigetaka Kumashiro,
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摘要:
AbstractA systematic design method for HBT's is described which is based on a two‐dimensional device simulator and a circuit simulator. The validity of this method has been studied by applying it to an AlGaAs/GaAs HBT with a base electrode sandwiched by two emitter electrodes. This structure has a performance better than that of a conventional structure. It is found that the designed values agree well with the measured results forhFE,CBE,CBCandfT. It is shown that the design accuracy offTandCBEcan be improved if the hot electron effect is introduced in the device simulator. A large signal modeling method is proposed by the circuit simulator SPICE‐F' which is modified so that the collector‐emitter offset voltage characteristic to the HBT can be expressed. By way of this new method, the bias dependence of equivalent circuit parameters of the HBT, such asfmax,fT,CBEandCBC, can be computed with good correlation with the experimental
ISSN:8756-663X
DOI:10.1002/ecjb.4420710409
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1988
数据来源: WILEY
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10. |
Coherent backscatter‐induced noise in optical fiber gyroscopes with serrodyne modulation |
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Electronics and Communications in Japan (Part II: Electronics),
Volume 71,
Issue 4,
1988,
Page 81-88
Yoichi Suzuki,
Eikichi Yamashita,
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摘要:
AbstractCoherent backscattered light produces considerable noise in optical fiber gyroscopes. The noise in serrodyne‐modulated optical‐fiber gyroscopes with a low‐coherence source is studied theoretically for various forms of serrodyne‐modulation functions. The noise in output signals from the lock‐in amplifier is analyzed for the closed‐loop gyroscope. The coherent backscatter‐induced noise against the maximum phase of serrodyne‐modulation is estimated for finite flyback time or exponential ramp. It is found that the ideal serrodyne‐modulation function with the maximum phase of π and without flyback time cancels the noise in the signals o
ISSN:8756-663X
DOI:10.1002/ecjb.4420710410
出版商:Wiley Subscription Services, Inc., A Wiley Company
年代:1988
数据来源: WILEY
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