摘要:

AbstractIntegrated circuits with 1GHz logic, 1G bit DRAM, and 1G transistors, together with the CMOS technology with a gate length of less than 0.2 μm are the ingredients of the “Giga‐Era.” However, in order to integrate these billions of MOSs at giga‐frequencies, the problem of the power consumption cannot be avoided. It is a common practice to cope with this problem by reducing the power supply voltage. In deep submicron MOS, although the basic gate delay is not likely to degrade as the power supply voltage is reduced, it is necessary to set a low threshold value (Vth) within the wafer plane with reduced parasitic devices, if the absolute current values become important, as in the interconnect load. However, reliability problems involving the short‐channel effect and hot carriers then cannot be avoided. This paper describes the use of the cobalt silicide process and shallow extension structure of the source/drain to reduce the parasitic resistance. It is also shown that setting a low Vthwith fewer fluctuations is possible by combining the double‐side‐wall process and the counter‐dose process. By means of the above process, deep submi‐cron CMOS with low parasitic resistance and low Vt

ISSN:8756-663X    

DOI:10.1002/ecjb.4420791101

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractNew forms of boundary integral equations are proposed for computer aided design (CAD) and simulation of near‐field optical circuits. These integral equations can be easily solved numerically by using the boundary element method or moment method without using complicated mode‐expansion techniques for open waveguide structures. As an example, the new equations are used to design a two‐dimensional optical particle manipulator, and the effectiveness and correctness are demonstrated by numerical re

ISSN:8756-663X    

DOI:10.1002/ecjb.4420791102

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractHigh performance under low supply voltage is required for ULSIs in combination with the higher packing density that results from scaling down to the deep sub‐micron region. For this requirement, the conventional method, using the DC hot carrier lifetime of MOSFETs as measured by DC stress, overestimates the degradation caused by real circuit operation. As a result, the improvement of MOSFET performance is limited by attempting to satisfy the overestimated hot carrier criteria under DC stress. Therefore, it is strongly desired that the reliability simulation estimate accurately hot carrier degradation in real circuit operation. We have found that the degradation rate depends on the stress conditions and can be expressed in terms of the difference between the gate and drain voltages. Hence, in this paper, we propose a new method of modeling and calculation of hot carrier degradation that incorporates this dependence and will demonstrate improved accuracy in predicting degradation and life time for both AC and DC bias conditions. We also propose a new duty ratio extraction method that can be used to predict the lifetime for hot carrier degradation under actual circuit operatio

ISSN:8756-663X    

DOI:10.1002/ecjb.4420791103

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractAn n‐n gate CMOS process with a minimum gate length of 0.15 μm was developed. By means of the epitaxial channel and the transient enhanced diffusion suppression, a shallow buried‐channel layer was realized. It is shown that there is an optimal thickness of the buried‐channel layer that maximizes the drain current, and that theVtstability is higher in the pMOS in which the channel is fabricated by epitaxy than the conventional pMOS fabricated by channel ion implantation. When the gate poly‐Si and the silicon layer selectively grown on the SD were silicide‐reacted with titanium, a low‐resistance gate electrode with an 0.15‐μm width and the low‐leak SD diffusion layer was realized. From the transistor characteristics obtained in the experiment, the circuit characteristics were simulated. It was found that the delay time of the inv

ISSN:8756-663X    

DOI:10.1002/ecjb.4420791104

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractAn experimental study of the frequency‐dependent dielectric properties of thermally aged polyaniline (pAn) films as a function of the concentration of the sulfuric acid solution used for dipping was performed. Inferring the morphological changes of the films from the results of ultraviolet‐visible (UV‐vis) and infrared (IR) absorption spectra and differential scanning calorimetry (DSC) ther‐mograms, the dependency of the dielectric properties of thermally aged films on the protonation level is discussed. The effects of thermal aging on dielectric properties may be subdivided into two temperature regions. In the temperature range lower than 170°C, the dielectric constant was decreased, especially at high frequencies, and the tan δ‐peak was shifted to lower frequencies with increasing aging temperature. The mobility of pAn chains and electric dipole appears to be gradually restricted with increasing temperature. In the range higher than 210°C, pAn cannot be protonated and the dielectric properties are unaltered by dipping in dilute sulfuric acid (pH = 2), owing to crosslink‐ing and oxidation of i

ISSN:8756-663X    

DOI:10.1002/ecjb.4420791105

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractOne of the important issues for the realization of deep, submicrometer CMOS is the choice between a buried channel or a surface channel for pMOS. Conventionally, buried‐channel devices have been considered difficult to miniaturize and operate at low voltage. This is because they have a distinct short‐channel effect and a large S‐swing (subthreshold swing). However, the conventional analysis considers only the case in which the buried layer is deep. The junction depth is reduced on miniaturization, but there has not been sufficient analysis for the case of a shallow buried layer. Therefore, we have analyzed by simulation the way in which the buried‐channel S‐swing and short‐channel effect depend on the depth of the buried layer and the source/drain junctions. We have found that if the buried layer is shallow enough for complete depletion, the S‐swing becomes smaller than that for a surface channel and the subthreshold characteristics become sharper. In other words, we have shown for the first time that the optimized structure for a minimum S‐swing is not a surface channel but a buried channel. This structure is called CDSC (counter‐doped surface‐channel). It is also demonstrated that the short‐channel effect can be suppressed better than in a surface channel if the source/drain is shallower than the buried layer. Therefore, CDSC is promising for deep

ISSN:8756-663X    

DOI:10.1002/ecjb.4420791106

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractIn order to analyze the BBT (band‐to‐band tunneling) phenomenon in flash memory cells by simulation, a new model is proposed, which improves on the BBT model by introducing the concept of “average electric field.” This model agrees well with the measured results in a wide drain N‐concentration range. Using this model, the reliability of memory cells is analyzed. It is found that the difference of the amount of BBT generation does not directly affect the endurance characteristics but does affect the disturb characteristics. The same model can be used to analyze problem points of the present cells and to estimate the BBT current of next‐generation devices

ISSN:8756-663X    

DOI:10.1002/ecjb.4420791107

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractThis paper discusses the influence of ion bombardment on the characteristics of SiN films. In this study, the double‐tube coaxial‐line microwave plasma CVD system, which is suitable for the investigation of ion bombardment, is used to deposit SiN films. The ion bombardment energy is varied by varying die RF bias at constant ion density. As the RF bias is increased, the film density increases and the hydrogen concentration decreases, but the dangling bond density increases. The increase in the film density and decrease of hydrogen concentration are caused by the increase in film surface temperature, while the increase of the dangling bond density is caused by bond breakage due to me N+ion implantation. When the substrate temperature is 200°C and the RFbias is −175 V, the film density is 3 g/cm3and the hydrogen concentration is 9 at.% because of the film surface heating effect of ion bombardment and also due to substrate heating. Substrate heating at 200°C suppresses the increase in the dangling bond density. It is also demonstrated that the film surface temperature is about 200°C when RF bias is −70–80 V and the substrate is unheated b

ISSN:8756-663X    

DOI:10.1002/ecjb.4420791108

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractIn this paper we derive a double‐tuned, narrow‐band transfer function and illustrate itsLCsimulation‐type active realization with low element sensitivity. First, a new double‐tuned function that is adjustable by a single parameter is derived for a circuit using mutual induction. Next, the basic circuit that generates negative feedback withRLCelements and controlled sources is derived. This basic circuit can have a low element sensitivity within the passband, as confirmed by the numerical analysis. As an example of the implementation for the basic circuit, an activeRCcircuit with the center frequencyf0= 455 kHz andQ= 30 is constructed; transistor gyrators are used forLelement simulation; and a single variable resistor is used for the coupling coefficient adjustment. The experimental tuned characteristics for several coupling coefficients are in good agreement with the calculated

ISSN:8756-663X    

DOI:10.1002/ecjb.4420791109

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY

摘要:

AbstractTa2N anodized capacitors have much greater heat resistance than Ta anodized capacitors. The difference between the heat resistances of the Ta and Ta2N capacitors was investigated by Auger analysis and it was found that the Ta2N compound thin film itself has a high heat resistance: Very little thermal oxidation of this film occurs until relatively high temperatures. The thermal degradation of TaN2anodized capacitors which takes place at temperatures above 450°C was found to be due to the oxygen diffusion from the anodized layer to the Ta2N underlayer. Another cause of thermal degradation was the oxidation of the Al electrode at high temperatures. Therefore, both the breakdown of the interface between the electrode and anodized layer and the oxidation of Al also contributed to the thermal degradation of the capacitors at high temperature. Even though the thickness of the Ta2N anodized layer was reduced by using a 30 V anodizing voltage, the heat resistance was greater and the capacitance was 3 times as high as that of Ta capacitors anodized at 160 V

ISSN:8756-663X    

DOI:10.1002/ecjb.4420791110

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1996

数据来源: WILEY