摘要:

The paper describes a circuit configuration which produces an output proportional to the logarithm of binary numbers presented at its input. The circuit is designed to process the first six significant digits only and can deal with binary numbers up to 220–1.The maximum output settling time, to within ½% of the final output level, is about 2 μs. The resolution of the circuit is limited by the number of digits taken; in the unit described it varies from one part in 32 to one part in 64 depending on the value of the binary number. This uncertainty amounts to a maximum of 0.22% of full-scale deflection. Other inaccuracies are small compared with the resolution errors. The circuit employs digital switching and uses linear components only. No devices with special characteristics are required.

DOI:10.1049/ree.1969.0014

出版商:IERE    

年代:1969

数据来源: IET