DOI:10.1049/ree.1980.0028

出版商:IERE    

年代:1980

数据来源: IET

摘要:

The development of large area c.c.d. image sensors is described and illustrated with the example ofa frame-transfer array with 385 × 576 image elements intended for 625-line television applications. The problems that still exist in meeting more demanding applications such as broadcast television are discussed and the various possible solutions are described.

DOI:10.1049/ree.1980.0029

出版商:IERE    

年代:1980

数据来源: IET

摘要:

This paper describes the operational features and performance of a fully-integrated programmable transversal filter (p.t.f.), using c.c.d./m.o.s.t. technology. The choice of filter architecture for a prototype realization is discussed with particular reference to a novel multiplier array implementation using a single, time-multiplexed m.o.s. transistor. The performance characteristics of a prototype, 64-point filter design based on this approach are detailed with reference to frequency- and matched- filtering. Techniques for optimizing the performance of this analogue filter structure under microprocessor control are suggested, through the iterative adaption of the filter impulse response, and equivalent results are given to show the improvement gained. An alternative technique for improving the filter characteristics which enables it to optimize the processing of signals under certain conditions has also been demonstrated. This adaptive filter configuration is based on the linear Widrow least-mean-square (W.l.m.s.) algorithm, and has been realized using the p.t.f. with minimal additional circuitry, without the requirement for a microprocessor.A general signal-processing module of 256-points using four cascaded filters is described; and results are presented when it is used in a sonar, matched-filtering experiment. Also a 64-point adaptive filter based on a prototype p.t.f. is described and its application to inverse filtering and self-tuning filtering is demonstrated.Finally, the potential of this miniature integrated filter for sonar-type applications is reviewed against new developments. In particular, a 256-point monolithic p.t.f.currently in development, and the concept of a dedicated adaptive filter in single chip form.

DOI:10.1049/ree.1980.0030

出版商:IERE    

年代:1980

数据来源: IET

摘要:

The paper reviews the various ways in which c.c.d.s can be employed in i.r. sensing systems. These include: (i) monolithic structures fabricated using narrow band semiconductors such as HgCdTe or InSb, extrinsic silicon structures doped with deep-level impurities, and silicon Schottky barrier devices; (ii) hybrid structures in which the c.c.d. is used as the read-out mechanism from an array of, for example HgCdTe, PbTe, or pyroelectric detectors. The relative merits of these different approaches are compared and recent experiment results for manystructures are quoted.

DOI:10.1049/ree.1980.0031

出版商:IERE    

年代:1980

数据来源: IET

摘要:

A 321 -cell c.c.d. bandwidth compressor capable of analogue sampling at 100 MHz is described. This system is designed to accept data with a bandwidth of 50 MHz and subsequently to clock the data out at rates up to 2 MHz for recording on magnetic tape via a cheap, low speed a-d converter. Since power requirements are at a premium, low overall power consumption and high speed performance were essential design goals. Details of the chip architecture are given and associated driver circuitry and preliminary experimental results described.

DOI:10.1049/ree.1980.0032

出版商:IERE    

年代:1980

数据来源: IET

摘要:

Substantial signal-to-clutter improvements are theoretically achievable using c.c.d.s to integrate a large number of returns. In practice, however, the performance of simple c.c.d. implementations is severely limited by charge transfer inefficiency, particularly if large range and high resolution are required. The paper describes several ways in which the effects of transfer inefficiency can be overcome or avoided.

DOI:10.1049/ree.1980.0033

出版商:IERE    

年代:1980

数据来源: IET

摘要:

The paper deals briefly with a few widely-used image signal processing algorithms and discusses how these can be incorporated on the same silicon chip as that of the c.c.d. scanner. Recent work on c.c.d. scanners is reviewed and solid-state scanners which include on-chip signal processing functions are described.Future trends are towards ‘smart’ scanners; these are scanners with on-chip real-time processing functions, such as analogue-to-digital conversion, thresholding, data compaction, edge enhancement and other real-time image processing functions.

DOI:10.1049/ree.1980.0034

出版商:IERE    

年代:1980

数据来源: IET

摘要:

The basic logic elements of AND, OR and INVERTER gates as implemented in c.c.d. logic are described and experimentally evaluated. The AND and OR gates are incorporated in one simple structure using the mechanism of charge spillage over a d.c. control gate from a common input well. Design equations are presented for the floating-gate master-slave sensing structure which is the basis of the inverter and are shown to be in good agreement with practical results. The problems associated with the devices, namely speed of operation and chargetorage under the slave, are discussed in detail.

DOI:10.1049/ree.1980.0035

出版商:IERE    

年代:1980

数据来源: IET