摘要:

Calculations of the thermal resistances of stripe-geometry double-heterostructure lasers are dependent on assumptions made concerning the positions of heat sources within the laser structures. The effect on thermal resistance of heat sources located at various levels in the multilayer structure are considered here. The calculations indicate that thermal resistances of proton-isolated structures can be approximately halved when energy is radiatively transferred from the device active region rather than when all heat is generated within the device active region. This should be taken into consideration when the experimental effectiveness of laser-dice-bonding technology is being evaluated.

DOI:10.1049/ij-ssed.1978.0007

出版商:IEE    

年代:1978

数据来源: IET

摘要:

The paper presents a 2-dimensional numerical model used to analyse the silicon-on-sapphire transistor under various geometries, doping levels and bias conditions. The model accounts for the thin-film structure and the finite interface charge at the silicon-sapphire interface. The model also includes the possibility of simulating nonisothermal effects, and is shown to be applicable to prediction of the transistor behaviour in the high-voltage region. The complete system of four coupled partial differential equations describing the internal behaviour of the s.o.s. transistor is solved exactly. Typical results for ann-channel double-implanted inversion-layer s.o.s. transistor are shown. The agreement between theory and experiment is found to be excellent.

DOI:10.1049/ij-ssed.1978.0008

出版商:IEE    

年代:1978

数据来源: IET

摘要:

A high-frequency power junction field-effect transistor with a nonplanar V-shaped channel fabricated by preferential etching of (100) silicon is described. The structure of the transistor is very simple; it requires only three photolithographic masking steps, and the result is a short-channel device with a high packing density. The theory of operation and the fabrication of this device are discussed, and the experimental characteristics of a 30-channel interdigitated structure having an effective channel length of 2.8μm, a channel width of 0.82cm and an active area of 0.1mm2are presented. This transistor exhibits a low-frequency transconductance of 87mS, a cutoff frequency of 1.2GHz and a power-dissipation density of 21W/mm2of chip area. The application of the transistor in a tuned power amplifier operating at 224 MHz is discussed.

DOI:10.1049/ij-ssed.1978.0009

出版商:IEE    

年代:1978

数据来源: IET

摘要:

Stressed operation ofp-channel m.o.s.t.s in the pre-avalanche region can cause the injection of hot electrons into the gate oxide adjacent to the source and drain junction. Trapping of this injected charge causes a localised reduction of the threshold voltage near the stressed junction and a consequent reduction of the effective channel length. Measurement of the saturated output conductance shows that the Early effect is much reduced after selective charge trapping. The phenomenon can be explained by regarding the stressed transistors as a composite device consisting of a number of series-connected m.o.s.t.s with differing threshold voltages, and can be used deliberately to reduce short-channel effects in small m.o.s.t.s.

DOI:10.1049/ij-ssed.1978.0010

出版商:IEE    

年代:1978

数据来源: IET

摘要:

An analytical i.g.f.e.t. model including drift and diffusion currents along the channel is developed. The theory, which is based on a gradual-channel approximation, is essentially equivalent to the double-integral formula by Pao and Sah, which provides correct results both in weak and in strong inversion. I.G.F.E.T. characteristics such as drain current, transconductance and output conductance are analytically expressed against the surface potential at the source and drain edges of the channel, which can be numerically evaluated in a few iterative steps. The model therefore seems suitable for c.a.d. applications.

DOI:10.1049/ij-ssed.1978.0011

出版商:IEE    

年代:1978

数据来源: IET