ISSN:0748-8017    

DOI:10.1002/qre.4680110402

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1995

数据来源: WILEY

摘要:

AbstractYield improvements can be achieved by both contamination control (manufacturing) and defect sensitivity decrease (design). In this paper, the need for critical area analysis is demonstrated for design based yield prediction and improvement. Experimental results for a typical CMOS process are provided.

ISSN:0748-8017    

DOI:10.1002/qre.4680110403

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1995

数据来源: WILEY

摘要:

AbstractParameters and their dependence on stress conditions are discussed using a three‐dimensional model, including all possible degrees of freedom. The results, applied to breakdown data for 10 nm oxide, reveal the upper limits for stress conditions. A physical explanation for the upper voltage limit is presented. Furthermore, the thermal activation energy and the slope of lifetime distributions (e.g., the shape factor β of the Weibull distribution) are investigated as functions of electric field and temperature. The results are compared to available literature da

ISSN:0748-8017    

DOI:10.1002/qre.4680110404

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1995

数据来源: WILEY

摘要:

AbstractAn in‐depth analysis of the write/erase degradation of source‐side injection flash EEPROM devices is performed, which reveals two mechanisms underlying this degradation: a decrease of the charge per cycle on the floating gate, accompanied by the series effect of oxide and interface charges locally trapped above the channel. In addition, the main disturb effects are characterized and shown to be non‐critical for reliable cell oper

ISSN:0748-8017    

DOI:10.1002/qre.4680110405

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1995

数据来源: WILEY

摘要:

AbstractThe current which flows through the metal semiconductor interface of an ohmic contact produces a Peltier effect. This thermal effect has been optically detected and used for the development of an optical ammeter, the determination of doping type of semiconductors and the homogeneity scanning upon integrated circuits.

ISSN:0748-8017    

DOI:10.1002/qre.4680110406

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1995

数据来源: WILEY

摘要:

AbstractA scanning force microscope (SFM) test system is used for voltage contrast studies on 0·5 μm integrated circuits. Waveform measurements are performed on passivated 0·5 μm conducting lines up to 4 GHz. Additionally two‐dimensional measurements at 10 MHz demonstrate the potential for device internal function and failure analysis in the sub‐μm regime by direct correlation between voltage contrast and quantitative topograph

ISSN:0748-8017    

DOI:10.1002/qre.4680110407

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1995

数据来源: WILEY

摘要:

AbstractThin oxide MOS capacitors are subjected to bipolar voltage stresses of different amplitudes and frequencies. According to a previously proposed breakdown model, the evolution of the current with the stress time has been considered to be due to the degradation of the oxide, i.e. to the generation and partial occupation of electron traps. When log(J) is represented versus the stress time, the slope of the plot and the magnitude of the current (which tends to decrease during constant‐voltage tests) are taken as indicators of the oxide degradation rate and degradation level, respectively. Our results suggest lower degradation rates, and consequently lower degradation levels for the same stress times, at high frequencies. This is consistent with the increase of time‐to‐breakdown with stress frequency observed by other authors, and confirms that, also for dynamic stresses, the relation between degradation and breakdown is fundamental to understand the physics of these phenomena. The slower degradation rates confirm the improvement of oxide reliability under dynamic AC stress condi

ISSN:0748-8017    

DOI:10.1002/qre.4680110408

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1995

数据来源: WILEY

摘要:

AbstractAs a prerequisite for predicting the soft‐error rate (SER) of CMOS circuits with dynamic registers a method to calculate the SER is presented which takes into account charge collection by drift and diffusion. It has been found that besides collection due to drift, the noise charge collected by diffusion has to be considered to accurately predict the SER of dynamic CMOS circuits. Calculated results are compared to device simulations and SER measurement

ISSN:0748-8017    

DOI:10.1002/qre.4680110409

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1995

数据来源: WILEY

摘要:

AbstractHot‐carrier effects pose a significant reliability problem in modern MOS processes. An accurate method of predicting hot‐carrier lifetimes is essential for the development of fine‐geometry MOS technology. A hot‐carrier degradation model developed by C. Huet al.at the University of Berkeley is widely used to predict device lifetimes at given operating conditions from the results of accelerated tests. This paper demonstrates a new method of performing hot‐carrier stress measurements which satisfies the key demand of this model. This method involves adjusting device drain voltage in order to maintain a constant ratio of substrate to drain currents. This method is employed to show that the Berkeley model makes a minimum lifetime prediction which is about an order of magnitude too short at accelerated stress conditions. This casts doubt on the suitability of the Berkeley model for use in circuit reliability simulation and for use in setting industrial reliability benchmarks. A new understanding of the importance of the gate‐source voltage during hot‐carrier reliability characterization using the Berkeley model is a

ISSN:0748-8017    

DOI:10.1002/qre.4680110410

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1995

数据来源: WILEY

摘要:

AbstractUsing a specifically developed measurement set‐up and a test structure typical for analogue applications, high precision measurements of the stress‐induced offset voltage degradation of differential pairs are presented. Extrapolation to operating conditions yields valuable information for analogue design in the sub‐micron CMOS r

ISSN:0748-8017    

DOI:10.1002/qre.4680110411

出版商:Wiley Subscription Services, Inc., A Wiley Company    

年代:1995

数据来源: WILEY