摘要:

The speed of a digital arithmetic processor depends essentially on the speed of the adders used in the system. Although Signed‐Digit Adders(SDA) are attractive, due to their parallel‐add capacity, economical arithmetic systems with low‐cost components and small fan‐out require a two‐step addition process using SD adders. This paper presents a new SDA design concept incorporating a conditional‐sum(KS) scheme that reduces the number of add operation required from two steps to one without an accompanying growth of fan‐in and fan‐out problems. The speed‐up ratio of the SD‐KS adder is expected to be as high asn:1 compared with conventional carry adders and 4:1 compared with the radix‐4 signed digit full adder array. Hardware complexity remains uniform in structure and at moderate levels. Various configurations are suggested to meet hardware complexity and speed requirements.

ISSN:0253-3839    

DOI:10.1080/02533839.1996.9677827

出版商:Taylor & Francis Group    

年代:1996

数据来源: Taylor

ISSN:0253-3839    

DOI:10.1080/02533839.1996.9677816

出版商:Taylor & Francis Group    

年代:1996

数据来源: Taylor