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11. |
Pascal circuit compiler for UK5000 |
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IEE Proceedings I (Solid-State and Electron Devices),
Volume 132,
Issue 2,
1985,
Page 116-120
C.R.Jesshope,
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PDF (631KB)
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摘要:
A Pascal compiler is described which can parse a limited subset of Pascal, and generates a circuit description in a format which can then be input to the UK5000 gate array software. A set of Pascal utilities completes this package by allowing the Pascal circuit description to be compiled by a standard Pascal system. This complete package allows the development of systems containing single or multiple UK5000 chips. Moreover this can be performed on any software development system. The use of Pascal as a hardware description language is not new, but this system promotes good top-down hierarchical design of UK5000 chips and also allows quick and efficient verification of the system, prior to the automatic generation of data for entry into the UK5000 system.
DOI:10.1049/ip-i-1.1985.0024
出版商:IEE
年代:1985
数据来源: IET
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12. |
Review of built-in test methodologies for gate arrays |
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IEE Proceedings I (Solid-State and Electron Devices),
Volume 132,
Issue 2,
1985,
Page 121-129
K.A.E.Totton,
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PDF (1199KB)
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摘要:
The paper presents a review of current and proposed test methodologies for semicustom gate arrays. The necessity of high quality testing is emphasised by considering some of the hazards and penalties associated with poor testability. The usefulness and limitations of testability analysis programs are then considered. A built-in test is introduced as an attractive alternative to conventional approaches based on automatic test pattern generation for highly structured circuits. This test technique is shown to offer significant benefits, including reduced test data volume, improved test quality, and easier maintenance testing. The advantages and disadvantages of three built-in test implementations for gate arrays are discussed. First, an architecture which combines anad hocdesign for testability with a comprehensive on-chip maintenance system is reviewed. This is followed by a presentation of an LSSD-based pseudorandom self-test and the associated test problems. Finally an exhaustive test, based on a similar architecture achieves a high quality test with guaranteed fault coverage. In conclusion, the future direction of test strategy development is predicted, in the context of increasing integration density and the convergence of ‘semicustom’ and ‘full-custom’ design styles.
DOI:10.1049/ip-i-1.1985.0025
出版商:IEE
年代:1985
数据来源: IET
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13. |
Impact and opportunities for application specific integrated circuits (ASICs) |
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IEE Proceedings I (Solid-State and Electron Devices),
Volume 132,
Issue 2,
1985,
Page 130-132
M.G.Penn,
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PDF (397KB)
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摘要:
The semiconductor industry has been responsible for initiating a new phase in the world's economic and industrial development. For more than two decades, average price (and cost) per function has decreased by 30%, industry growth has averaged nearly 20% per year. Each year more memory bits are sold than in all the previous years added together. In the 35 years since the birth of the transistor, the semiconductor industry has undergone several phases. In the 1960s there was the integrated circuit, which, in turn, spawned the memory and microprocessor revolution of the 1970s. Until the 1980s the semiconductor industry had been dominated by standard parts, albeit of ever increasing complexity. In the 1980s, the electronics industry entered a new era: that of the application specific IC (ASIC). This came about through a combination of improved IC design techniques, processing and software capability. The paper reviews the events that led to this change and discusses some of the opportunities it presents.
DOI:10.1049/ip-i-1.1985.0026
出版商:IEE
年代:1985
数据来源: IET
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