摘要:

The basic design criteria for high-power gate turn-off (GTO) thyristors are discussed. Results of a Study of the influence of thep-base on gate avalanche voltage show that only a narrow range of voltages are possible. The importance of the cell array in determining debiasing effects on the gate electrode, and its effects on gate current density, are illustrated. Finally, the switching performance of 2500 V and 4500 V GTO thyristors with varying anode shorting efficiencies is examined.

DOI:10.1049/ip-i-1.1985.0053

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The integration of a monolithic antiparallel diode into the inactive cathode bond-pad area of a gate turnoff thyristor (GTO) has been investigated with computer modelling followed by experimental work, using as a vehicle the BTV60, a 120A GTO optimised for AC motor control. It is shown that this is feasible and is especially suitable for second generation GTO technology (fine interdigitation, unshort-circuited anode, lightly gold-killed), with the diode having the right characteristics in forward voltage drop and reverse recovery. The resulting devices performed well in tests and may lead to considerable simplification and cost reduction in motor control circuits.

DOI:10.1049/ip-i-1.1985.0054

出版商:IEE    

年代:1985

数据来源: IET

摘要:

A model is presented for the operation of MOS transistors which is applicable to many power and short channel devices. This improved 1-dimensional charge control model allows for the effects of the mobility reduction due to the gate-channel field and to velocity saturation of the channel carriers under the high drainsource field. Experiments have verified the model fornandpchannel devices. The high drain voltageID/VGdata are compared with the model predictions using accepted experimental values of the bulk saturation velocity and velocity-field curves together with experimental measurements of the channel series resistance and the gate-field reduction of the mobility.

DOI:10.1049/ip-i-1.1985.0055

出版商:IEE    

年代:1985

数据来源: IET

摘要:

A short review of the history and modelling of Schottky structures is given. A one-dimensional numerical model including tunnelling and avalanche breakdown effects for the Schottky structures is described. Simulation results on complementary power Schottky structures for the three different barrier heights (data for Cr, W, Al) are carried out for DC and transient response.

DOI:10.1049/ip-i-1.1985.0056

出版商:IEE    

年代:1985

数据来源: IET

摘要:

A Schottky barrier diode with field relief p+-rings which modify the surface field in the device is described. The leakage reduction per unit area is a function of geometry and for the smallest ring spacing amounted to a factor of approximately 10. The data were fitted to a simple theory of the field reduction expected from the geometrical considerations. The limits of the technique are discussed.

DOI:10.1049/ip-i-1.1985.0057

出版商:IEE    

年代:1985

数据来源: IET

摘要:

A 1200 Vn-channel insulated gate transistor (IGT) has been designed and evaluated. To reduce the Miller capacitive coupling of the input and the output terminals during the transient conditions, the terraced gate design has been implemented. As a result, the Miller capacitance is lowered 4–5 times compared to conventional gate design. Also, the gate pad is placed at the centre of the pellet so that the intrinsic device turnon and turnoff times can be shorter. To prevent current crowding and thermal fatigue around a single emitter pad, a multiple emitter pad design scheme is adopted. The 1200 Vn-IGTs have reached up to 114 A latch-up current at 150°C.

DOI:10.1049/ip-i-1.1985.0058

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The use of gallium arsenide for power devices has recently been the subject of a number of papers. The paper examines the properties of gallium arsenide relevant to power device behaviour together with published results on power devices made in gallium arsenide.

DOI:10.1049/ip-i-1.1985.0059

出版商:IEE    

年代:1985

数据来源: IET

摘要:

A general boundary determined equation is used to obtain the physical asymptotes for the current density of PIN diodes. Application of this equation indicates that lower level injection regions are degenerate versions of the higher level regions. Other methods depend upon precise knowledge of the carrier density profile whereas the present approach only requires a notional indication of the ratio of minimum to boundary carrier densities. This ratio is an important determining factor for the gradient of boundary carrier density which exerts a strong influence upon boundary current density. A theoretical basis is laid which explains the link between the various ranges of injection level. This asymptotic approach could provide an effective method in applying charge control models for transient analysis over wide ranges of current.

DOI:10.1049/ip-i-1.1985.0061

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The transient forward voltage drop of fast diodes for medium power circuits is investigated using a computer model. Fast diodes, of bothpnand PIN structures, are experimentally examined for a range of electrical and physical parameters. A multiple curvilinear statistical regression was used on the results and an empirical relationship is presented.

DOI:10.1049/ip-i-1.1985.0062

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The paper describes the way a semiconducting coating, such as SIPOS, controls the spread of the depletion region near the surface of simple planar high-voltage diodes. This is important to achieve the optimum breakdown performance for high-voltage devices. When an insulating oxide separates the SIPOS from the silicon, the surface layer acts as a resistive field plate and spreads a thin depletion region right across the surface at only a few volts reverse bias. Without the oxide, or if it is thin enough to be effectively transparent to electrons and holes, the depletion region spread in the surface is limited by current flow across the SIPOS silicon interface, and the depletion spread with bias becomes more like that expected for bulk silicon. For reverse biased planar diodes, with SIPOS directly over the junction, the leakage current is proportional to the voltage to the power of 0.7–0.8 when measured at temperatures where the current through the SIPOS dominates. These effects can be modelled, neglecting any effect from thep–njunction, using lateral and vertical SIPOS-silicon interface current measurement data.

DOI:10.1049/ip-i-1.1985.0063

出版商:IEE    

年代:1985

数据来源: IET