摘要:

Equivalent circuits for two high-frequency transistors in the range 40–1200 MHz have been determined. The circuit is extended for different bias conditions by varying certain parameters of the model.

DOI:10.1049/ip-i-1.1985.0045

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The sidewall space-charge region of an emitter-base junction is of importance in the determination of low current gain fall-off where both bulk and surface recombination dominate. The paper discusses the behaviour of this region using results from two different numerical analyses. A previously defined modelling parameter to represent surface recombination effects is computed from physical data and the contribution to recombination currents from three distinct regions (surface, bulk sidewall and bulk vertical) is compared. Experimental determination of the parameter is discussed and values given for a typical process.

DOI:10.1049/ip-i-1.1985.0046

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The paper describes five different emitter-coupled logic (ECL) bistable designs and their comparison, both in the divide by 2 and transmission modes of operation, using computer simulation techniques. By adopting a single transistor model, performance differences due to processing variations have been eliminated. Factors affecting the operating rate of a bistable are discussed, and the simulations show one design to have the fastest maximum toggle frequency of 920 MHz, and a different one the shortest average slave output transition time of 400 ps. The optimum design is a balanced bistable with single emitter follower level shifting between stages. This has been fabricated using the BTRL ECL 40 process, and measurements show that the maximum transmission rate is 1 Gbit/s.

DOI:10.1049/ip-i-1.1985.0047

出版商:IEE    

年代:1985

数据来源: IET

摘要:

A MESFET design with a shallow gate trench that slopes towards the source is proposed. Its characteristics have been simulated by means of the Monte Carlo particle model and compared to those of a planar and uniformly recessed gate structure of similar geometry. The sloped gate should reduce the resistance in the conduction channel and improve the noise figure. It is found that this device combines the good unilateral gain of the planar device and the low intrinsic minimum noise figure of the best uniformly recessed gate transistor. In uniformly recessed gate structures it was found that the length of the gate is important in reducing the noise: by shielding the source field fluctuations from the drain field ones it is possible to reduce the minimum noise figure. The simulation comprises both the DC and the AC characteristics. The latter is obtained around an operating point chosen with the drain biased at saturation. The distributions of fields and carriers for the sloped gate device have been plotted at this point and the equivalent circuit elements extracted.

DOI:10.1049/ip-i-1.1985.0048

出版商:IEE    

年代:1985

数据来源: IET

摘要:

Microelectronic ion sensors based on monolithic silicon integrated circuit (IC) and hybrid circuit technologies have been the subject of considerable research and development over the past 15 years. This paper reviews the conceptual background and history of both kinds of device, comparing their operation with those of conventional ion-selective electrodes and coated-wire electrodes. Attention is focused on the interfacial processes involved in the ion-sensing mechanism of microelectronic devices, with particular reference to the significance of models based on either ideally blocking or nonblocking mechanisms. This is a matter which has important theoretical and practical consequences for both silicon IC-based microelectronic sensors such as the ionsensitive field-effect transistor (ISFET) and hybrid circuit based devices. Practical problems associated with effective encapsulation and the provision of a suitable reference electrode are also considered.

DOI:10.1049/ip-i-1.1985.0050

出版商:IEE    

年代:1985

数据来源: IET