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| 11. |
Simple high-frequency CMOS transconductor |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 470-474
S.P.Singh,
J.V.Hanson,
J.Vlach,
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PDF (471KB)
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摘要:
A new transconductor, using only two transistors, is presented. It is based on standard inverter configurations and does not need matching ofnMOS andpMOS transistors or of the power supply voltages. Reduction in nonlinearity is achieved by maintaining a zero offset condition. The circuit is not affected by variations in body effect as sources and substrates are connected to fixed voltages. Although the inverter has a low signal level handling capability (≃300mV for a total harmonic distortion of 1%), this can be improved by the use of two inverters. This leads to a larger dynamic range and has no noticeable effect on bandwidth.A wideband integrator is developed, based on the new transconductor, with independent adjustment of quality factor and unity-gain frequency.
DOI:10.1049/ip-g-2.1990.0072
出版商:IEE
年代:1990
数据来源: IET
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| 12. |
Oxide breakdown in a metal-SiO2-Si capacitor: influence of the metal electrode |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 475-478
G.Sarrabayrouse,
J.L.Prom,
K.Kassmi,
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PDF (352KB)
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摘要:
The influence of the metal electrode, size, type and thickness on the breakdown field strength of a metal-SiO2-Si capacitor with an insulating layer less than 100 Å thick is investigated. The results are interpreted in terms of stress at the SiO2-Si interface.
DOI:10.1049/ip-g-2.1990.0073
出版商:IEE
年代:1990
数据来源: IET
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| 13. |
Current-controlled linear MOS earthed and floating resistors and their application |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 479-481
Z.Wang,
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PDF (379KB)
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摘要:
A current-controlled linear MOS earthed resistor that requires only three transistors is realised by means of a new linearisation technique. A nonlinearity within ±1.5% full scale in the 0–4V voltage range for a 5V supply is experimentally achieved with discrete MOS devices. However, much higher linearity can be expected if we choose the ratio of two transistor sizes exactly, according to the derivation in the paper. A floating resistor, derived from the earthed one, is also presented.
DOI:10.1049/ip-g-2.1990.0074
出版商:IEE
年代:1990
数据来源: IET
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| 14. |
Testing of interconnection circuits in wafer-scale arrays |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 482-488
Y.-H.Choi,
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PDF (1029KB)
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摘要:
An efficient testing algorithm for interconnection circuits, including programmable switches and data links in wafer-scale reconfigurable arrays, is presented. Faulty programmable switches or data links are eliminated by finding fault-free paths in the switch grid obtained by isolating all computing units from the rest of a reconfigurable array. No internal test points are assumed. The algorithm is shown to achieve very high performance, even if cell yield is low.
DOI:10.1049/ip-g-2.1990.0075
出版商:IEE
年代:1990
数据来源: IET
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