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| 11. |
Efficient implementation ofNth-band FIR filters based on a simple window method |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 4,
1990,
Page 302-308
V.Anastassopoulos,
T.Deliyannis,
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PDF (733KB)
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摘要:
A simple method is proposed for designingNth-band FIR filters with reduced hardware. This is achieved by making special use of the Kaiser window so that most of the filter coefficients will be related to each other by the simple relationship 1:2. Filter selection and design is simplified by means of data tables and a specially written selection program. Filter implementation both in PCM and delta modulation is proved advantageous compared with standard design methods.
DOI:10.1049/ip-g-2.1990.0046
出版商:IEE
年代:1990
数据来源: IET
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| 12. |
CMOS operational amplifier with nearly constant settling time |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 4,
1990,
Page 309-314
R.Klinke,
B.J.Hosticka,
H.-J.Pfleiderer,
G.Zimmer,
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PDF (734KB)
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摘要:
An operational amplifier with a settling time nearly independent of the signal amplitude and the capacitive load has been realised in CMOS technology. It uses an additional circuit to inject an extra bias current into the bias circuit of the operational amplifier. This measure substantially increases the slew rate of an operational amplifier for a given quiescent current. It is useful for programmable high-frequency switchedcapacitor circuits, because it always yields an optimum performance without any tailoring.
DOI:10.1049/ip-g-2.1990.0047
出版商:IEE
年代:1990
数据来源: IET
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| 13. |
Generation of ordered subcircuits for an automatic sizing program |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 4,
1990,
Page 315-318
D.Howard,
L.T.Walczowski,
W.A.J.Waller,
M.H.Smith,
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PDF (601KB)
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摘要:
The design of increasingly complex integrated circuits requires synthesis tools rather than analysis tools. A tool that calculates transistor sizes is useful both to design a new circuit and to move an existing design to another process. The paper describes an algorithm that can be used in such a program to structure an otherwise unstructured array of unsized transistors in a CMOS digital circuit. This structure is related to the functionality of the circuit, so that the sizing model is provided with all the information required. The paper then goes on to discuss how the ‘subcircuits’ were ordered so that they could be sized, taking the necessary factors into account
DOI:10.1049/ip-g-2.1990.0048
出版商:IEE
年代:1990
数据来源: IET
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| 14. |
Ideal limiter in the presence of wide bandwidth noise |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 4,
1990,
Page 319-322
J.Siuzdak,
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PDF (337KB)
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摘要:
The performance of an ideal hard limiter in the presence of wide bandwidth noise is investigated in a simplified way. The output noise spectral density near zero frequency is of primary interest since it determines the performance of a system using hard limiters such as in a PLL. It is shown that this spectral density is a function of the input SNR and the noise bandwidth. The theoretical results are verified by measurement.
DOI:10.1049/ip-g-2.1990.0049
出版商:IEE
年代:1990
数据来源: IET
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