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1. |
Switch-level timing verification for CMOS circuits: a semianalytic approach |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 405-412
H.-G.Yang,
D.M.Holburn,
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摘要:
The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.
DOI:10.1049/ip-g-2.1990.0062
出版商:IEE
年代:1990
数据来源: IET
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2. |
Efficient systolic high speed architectures for delayed multipath two-dimensional FIR and IIR digital filtering |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 413-423
H.K.Kwan,
M.T.Tsim,
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摘要:
In the paper, two novel efficient blocklevel systolic architectures for the high speed realisation of delayed multipath two-dimensional FIR and IIR digital filters are presented. In practice, difficulty arises in the implementation of an IIR digital filter because of the inherent timing constraint in its recursive loop. With the new transformation method presented in the paper, an extra loop delay is allowed in the recursive part of the multipath structure of an IIR digital filter. Consequently, the problem of the inherent timing constraint in the recursive loop is solved. Two methods for the stabilisation of the transformation method are also introduced. The resultant blocklevel systolic structures remove the global communication requirements, which further increases the efficiency of the final realisation.
DOI:10.1049/ip-g-2.1990.0063
出版商:IEE
年代:1990
数据来源: IET
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3. |
Chebyshev phase networks for pulse compressing and stretching |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 424-426
B.M.Djurich,
R.A.Petkovich,
O.D.Djurdjanovich,
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PDF (315KB)
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摘要:
A method for the direct synthesis of filters for pulse compressing and stretching, the phase of which approximates a Chebyshev squared phase in an arbitrary frequency region, is described. The procedure is based on the solution of a linear equation system that provides a final solution within a very small number of iterative cycles.
DOI:10.1049/ip-g-2.1990.0064
出版商:IEE
年代:1990
数据来源: IET
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4. |
Design of 2-D recursive filters with asymmetric half-plane lattice modelling |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 427-438
A.H.Kayran,
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PDF (1008KB)
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摘要:
A method, based on 2-D asymmetric half-plane lattice parameters, for the design of two dimensional (2-D) recursive digital filters is presented. The design procedure calculates the lattice parameter factors from the prescribed frequency characteristics. The order of the design is controlled by ana priorierror criterion, corresponding to the minimum mean squared error between two successive stages. The stability of the resulting filter is determined at each successive lattice stage from the computed 2-D reflection factors. The capabilities of the proposed approach are demonstrated by the design of a fan filter and circularly symmetric lowpass filter. The computer time for their design is of the order of seconds for both filters.
DOI:10.1049/ip-g-2.1990.0065
出版商:IEE
年代:1990
数据来源: IET
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5. |
Active and digital ladder-based allpass filters |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 439-445
Li Ping,
J.I.Sewell,
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PDF (674KB)
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摘要:
Ladder-based allpass filters are extended for activeRLC, activeRC, SC and digital realisations. The resulting circuits have the attractive properties of parallel structure and very low amplitude sensitivity to component changes. The analogue implementations are canonical with respect to the number of op amps and the digital ones are multiplier canonic. Detailed examples are given for SC designs and these are critically assessed for capacitance spread and sensitivity.
DOI:10.1049/ip-g-2.1990.0066
出版商:IEE
年代:1990
数据来源: IET
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6. |
Real number arithmetic for mixed behavioural and structural descriptions |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 446-450
M.G.Hill,
N.E.Peeling,
I.F.Currie,
J.D.Morison,
E.V.Whiting,
C.O.Newton,
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摘要:
The paper describes extensions to the ELLA system for specifying hardware circuits containing mixed behavioural and structural real arithmetic, from the highest abstract level down to bit level. A consequence of these extensions is the provision of an extensive set of logical and arithmetic operators on arbitrary length arrays of bits in both signed and unsigned format. The paper outlines the rationale used in the development and shows how the extensions can be used to access the host's own operators.
DOI:10.1049/ip-g-2.1990.0067
出版商:IEE
年代:1990
数据来源: IET
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7. |
Safe sequencing of concurrent events in behavioural simulation |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 451-458
F.Curatelli,
G.M.Bisio,
E.Di Zitti,
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摘要:
A functional/behavioural simulator is described, in which the system to be simulated is modelled by defining its hierarchy and by specifying the descriptive function of the behaviour of its components. The functional model, based on the definition ofstrictandnonstrict functions, makes it possible to introduce and formally justify a simulation mechanism for safe sequencing of concurrent events in the presence of zero-delay components. Static and dynamic component instances are allowed, and the system can be simulated at different hierarchical levels, specified by the user for each component. The simulation algorithm is based on an event-driven mechanism and has been implemented in the language C.
DOI:10.1049/ip-g-2.1990.0068
出版商:IEE
年代:1990
数据来源: IET
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8. |
Modelling of the sidegating and the backgating effects in GaAs MESFETs |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 459-462
H.L.Kwok,
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PDF (522KB)
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摘要:
Sidegating and backgating effects affect theI/Vcharacteristics of a GaAs MESFET built on SI substrates. The basic charge trapping process can be related to current flowing through the channel-substrate interface. This effectively changes the channel thickness. For the side-gating effect, the observed voltage threshold for current pinch-off is explained by the breakdown of a parasitic lateralnpntransistor. An equivalent circuit model is put forward to include the sidegating and backgating effects. Reasonable results have been obtained during simulation.
DOI:10.1049/ip-g-2.1990.0069
出版商:IEE
年代:1990
数据来源: IET
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9. |
Effects of cathode lengths and epitaxial layer widths onn1+n1−δ(p+)n2−n2+p+andn1δ(p+)n2p+switching devices |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 463-466
A.Al-Bustani,
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PDF (356KB)
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摘要:
The paper describes the effects of then1-cathode length and then2-epitaxial layer width on theI/Vcharacteristics of two-state homojunctionn1−π1−(p+-plane) – π2−n2−p+andn1-(p+-plane)-n2-p+structures. Both devices are regenerative bulk unipolar switches (BUS) in which thep+injector modulates the internal barrier and hence modify the switching and holding parameters. It is found that the switching and holding points parameters decrease as the cathode lengthlkoincreases, and increase as the epilayer widthl0increases. A comparison with existing experimental data is also presented.
DOI:10.1049/ip-g-2.1990.0070
出版商:IEE
年代:1990
数据来源: IET
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10. |
Analysis of focused surface wave transducers |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 6,
1990,
Page 467-469
M.Kirci,
E.Akcakaya,
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PDF (260KB)
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摘要:
A new acoustic field analysis, based on the Huygens principles, is given for an elastic surface acoustic wave convolver, made by using a focused transducer on a YZ-LiNbO3piezoelectric crystal. In the acoustic field analysis, a new slowness function approximation is suggested for the anisotropy of the medium, instead of the conventional parabolic slowness function. The acoustic field analysis obtained by using this function is compared to the other analysis techniques and the results are discussed.
DOI:10.1049/ip-g-2.1990.0071
出版商:IEE
年代:1990
数据来源: IET
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