摘要:

A simple procedure for the design of a Chebyshev rational function is presented. Extremes of the equiripple magnitude function are defined by the accepted orthogonal polynomial, the ‘ minimum property’ of which guarantees a good group delay characteristic and small transient overshoot. A single parameter allows us to compromise between a broad bandwidth and a good group delay characteristic without changing the magnitude of the ripples. When compared with the published maximally flat approximations, the presented function proved superior in both the frequency and time domains.One of the possible applications of such rational functions, in the design of equalisers to cancel the effects of parasitic reactances, is discussed.

DOI:10.1049/ip-g-2.1990.0036

出版商:IEE    

年代:1990

数据来源: IET

摘要:

In the paper, a new circuit element, termed a current limiter, is introduced. A technique based on the use of the current limiter is then proposed for the realisation of nonlinear resistances. Floating and earthed nonlinear resistances, working in both a voltage-controlled mode and a current-controlled mode, can be implemented in such a realisation scheme. The design principle is suitable for implementation in monolithic integrated form. Experimental results showing the accuracy and linearity of the circuits are also presented.

DOI:10.1049/ip-g-2.1990.0037

出版商:IEE    

年代:1990

数据来源: IET

摘要:

The discrete version of a theorem due to Huang is presented and is then used to demonstrate that the window method is effective for the design of 2-D circularly symmetric nonrecursive filters with abitrary piecewise-constant amplitude responses. The window method is then shown to be applicable to the design of quadrantally symmetric 2-D filters, such as fan filters. The paper concludes with an example that illustrates that fairly good results are obtained, with minimal design effort and computation.

DOI:10.1049/ip-g-2.1990.0038

出版商:IEE    

年代:1990

数据来源: IET

摘要:

The work is intended to give system designers an impression of the bit rates that will be achievable with the various electronic components of future optical fibre transmission systems if silicon bipolar technologies are applied. To this end, basic ICs were simulated and designed on the basis of a state-of-the-art laboratory technology. As has already been shown in an earlier work [1], there is a large variation in maximum achievable speeds between the different electronic components, but most of them are expected to work at 10 Gbit/s, some of them even at 20 Gbit/s and above. The most problematic component in 10 Gbit/s long-haul trunk lines will be the preamplifier because of the high-sensitivity (i.e. low-noise) requirements. The modelling and design techniques used were successfully checked by comparing the simulated and measured results of a static 15 GHz frequency divider produced with the same technology.

DOI:10.1049/ip-g-2.1990.0039

出版商:IEE    

年代:1990

数据来源: IET

摘要:

It is shown that for bit-level pipelined processors whose elements require no precharge phase, pipelining with master-slave latches gives a theoretical maximum throughput of nearly twice that of the Mead-Conway alternating phase arrangement. A comparison is made between area and power requirements as a function of clock rate, both in general terms and with reference to a design example; a pipelined multiplier implemented as a bit-level systolic array.

DOI:10.1049/ip-g-2.1990.0040

出版商:IEE    

年代:1990

数据来源: IET

摘要:

A new design methodology for knowledge-based analogue IC design is presented. Due to the nonlinear nature of the analogue design process, iterations are always necessary to achieve accurate and reliable designs. A prototype expert system design assistant and a conventional circuit simulator are used for the iterative design process. The expert system employed is capable of optimising circuit topologies, as well as circuit element geometries, to better satisfy the performance specifications. Circuit reconstruction is achieved through circuit primitive replacements and design equation substitutions. Circuit primitive and critical nodes are processed before layout generation to minimise undesired parasitic effects. Layout parasitics can be included optionally in the design optimisation step. Experimental results are shown, to demonstrate the effectiveness of the flexible architecture approach through iteration and the expert analogue design system.

DOI:10.1049/ip-g-2.1990.0041

出版商:IEE    

年代:1990

数据来源: IET

摘要:

A new and simple method using device simulation results to determine the geometric dependences of the zero-bias threshold voltage and body-effect coefficient for submicrometre MOS transistors is presented. Noa priorigeometric shape of the bulk depletion region is assumed. The threshold-voltage reduction and body-effect coefficient were experimentally determined to have a linear and exponential dependence on 1/Leff, respectively, for submicrometre LDD MOS transistors with effective channel length as small as 0.22 μm.

DOI:10.1049/ip-g-2.1990.0042

出版商:IEE    

年代:1990

数据来源: IET

摘要:

A novel new event-driven MOS timing simulator for VLSI circuits, EMOTA, is presented. The traditional event-driven simulation scheme used in logic simulation is modified for use in this circuit level timing simulator. The fast performance is due to the result of mixing the new derived event-driven algorithm and its associated time-wheel control mechanism, together with the unidirectional nonlinear Gauss-Seidel relaxation technique to decouple the circuit equations. EMOTA allows both interactive and batch simulation modes and its input format is the same as SPICE. The simulation speed of EMOTA is shown to be more than 300 times faster than SPICE2G.5 for circuits of several hundred transistors and the simulated waveforms have acceptable accuracy.

DOI:10.1049/ip-g-2.1990.0043

出版商:IEE    

年代:1990

数据来源: IET

摘要:

A simple analytical model for the lateral electric field in the drain region is developed for an LDD MOSFET. A quasi-two-dimensional analysis is employed to derive this model under the assumption of a two-dimensional doping profile of the LDD region. The results obtained by the model agree well with the two-dimensional PISCES [1] simulations of the electric field in the drain region. Furthermore, the format of the model is readily implementable in a circuit simulator to better understand the mechanisms involved in reducing the electric field in the LDD region with respect to circuit optimisation. Results show the behaviour of the electric field under the influence of the length and doping concentration of the LDD region. Influence of the oxide thickness and junction depth are also accounted for by the model.

DOI:10.1049/ip-g-2.1990.0044

出版商:IEE    

年代:1990

数据来源: IET

摘要:

The functional architecture of a matrix product machine is described. The machine consists of a set of three custom VLSI chips and a RAM array. Machine performance is 140 Mflops for matrix products. A transformation of the DFT is presented that maps well onto this machine. Performance comparisons with both new architectures and commercial products demonstrate that the matrix product machine is faster over a wide range of transform lengths.

DOI:10.1049/ip-g-2.1990.0045

出版商:IEE    

年代:1990

数据来源: IET