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1. |
Harmonic distortion of the four-terminal MOSFET in non-quasistatic operation |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 5,
1990,
Page 325-332
L.-J.Pu,
Y.P.Tsividis,
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摘要:
This paper deals with the large-signal analysis of four-terminal MOS transistors from DC to frequencies where the operation is nonquasistatic. The numerical evaluation of harmonic distortion in such operation is considered. The results presented are verified through comparisons with measurements and provide (a) a sensitive indicator of how well the device physics is modelled, (b) benchmark results against which to compare future work on computationally efficient models and (c) an initial understanding of distortion in non-quasistatic operation, for circuit design purposes.
DOI:10.1049/ip-g-2.1990.0052
出版商:IEE
年代:1990
数据来源: IET
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2. |
Operational amplifier modelling for high speed sampled data applications |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 5,
1990,
Page 333-339
C.A.Makris,
C.Toumazou,
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PDF (743KB)
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摘要:
A pair of symmetrical and versatile equivalent circuits suitable for two pole single and two stage operational amplifiers is presented. The improved accuracy of the new equivalent circuits is necessary when designing the compensation network of high speed amplifiers to minimise their very strongly phase-dependent settling time, which is important for sampled data analogue signal processing circuits. These models also identify a critical effective capacitance, which is shown to govern the settling behaviour of the operational amplifier.
DOI:10.1049/ip-g-2.1990.0053
出版商:IEE
年代:1990
数据来源: IET
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3. |
Mathematical techniques for low-cost optimisation of digital MOS circuits |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 5,
1990,
Page 340-344
B.Hoppe,
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PDF (749KB)
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摘要:
In the paper, optimisation methods for MOS VLSI digital circuits are discussed. Typically, signal delay, chip area and power dissipation are the optimisation criteria. Since they are in conflict, complex multiobjective programming problems have to be solved. Novel mathematical methods are presented, which allow for a complete and accurate solution at low computational cost. The new methods guarantee that only the relevant global design optima are calculated. There is no confusion with solutions that are only of local optimality. This reduces the numerical effort and eliminates convergence problems found for other algorithms.
DOI:10.1049/ip-g-2.1990.0054
出版商:IEE
年代:1990
数据来源: IET
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4. |
Sorting without exchanges on a bit-serial systolic array |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 5,
1990,
Page 345-352
G.M.Megson,
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摘要:
In the paper, a number of bit-serial systolic designs for ordering a list ofnelements without ‘on-the-fly’ exchanges are considered. The algorithms require 4n+p+kbit steps wherep= log2nandkis the number of bits required to encode all the possible elements. The arrays requireO(n(p+k)) bit cells with a complexity roughly the same as that of a full adder and between max (p,k) andp+kinput/output pins. The input to the array is the list to be sorted and an auxiliary vector whose elements have bit lengthp. The output, is the list itself and the auxiliary vector, which is updated to produce pointers to the correct position of each element in the ordered list.
DOI:10.1049/ip-g-2.1990.0055
出版商:IEE
年代:1990
数据来源: IET
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5. |
‘Winner-take-all’ circuit for neurocomputing applications |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 5,
1990,
Page 353-359
R.Perfetti,
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摘要:
In the paper a parallel analogue implementation of the ‘winner-take-all’ function is proposed. It can be utilised in the hardware realisation of neurocomputer systems based on competitive learning, which find application in areas such as pattern classification, vector quantisation and image recognition. Analytic results are derived by means of the piecewise-linear method in the case of two variables and SPICE simulation results are presented in the general case. It is shown that the circuit exhibits somead hocproperties that make it well suited for this kind of application.
DOI:10.1049/ip-g-2.1990.0056
出版商:IEE
年代:1990
数据来源: IET
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6. |
Necessary and sufficient conditions for strictly positive real matrices |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 5,
1990,
Page 360-366
G.Tao,
P.A.Ioannou,
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摘要:
In this paper we present some useful properties of strictly positive real transfer matrices for both continuous and discrete-time linear time-invariant systems in the frequency and state space domains. Some of these properties follow from known results and are presented for the sake of completeness. The new results obtained are mainly for discrete-time systems and include the discretetime version of the Lefschetz-Kalman-Yakubovich lemma for transfer matrices.
DOI:10.1049/ip-g-2.1990.0057
出版商:IEE
年代:1990
数据来源: IET
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7. |
Synthesis of efficient low-order FIR filters from primitive sections |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 5,
1990,
Page 367-372
G.Wade,
P.Van-Eetvelt,
H.Darwen,
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PDF (678KB)
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摘要:
A synthesis procedure for low-order FIR filters based on the cascading of computationally simple (and in some cases very computationally efficient) primitive sections is described. An integer programming approach effectively yields an optimal factorisation of a low-order transfer functionH(z) that satisfies the filter specification and, hence, yields also an optimal cascade of available primitives. If the primitive cascade approach is used, synthesised filters are considerably more computationallly efficient than optimal direct form realisations. The design process is noniterative, completely automatic and particularly suitable for high sample rate applications.
DOI:10.1049/ip-g-2.1990.0058
出版商:IEE
年代:1990
数据来源: IET
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8. |
Computation of prime factor DFT and DHT/DCCT algorithms using cyclic and skew-cyclic bit-serial semisystolic IC convolvers |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 5,
1990,
Page 373-389
S.Gudvangen,
A.G.J.Holt,
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摘要:
The paper presents the results of a study of the use of cyclic and skew-cyclic convolvers for the evaluation of the subspace discrete Fourier transforms (DFT) and discrete Hartley transform (DHT) modules resulting from a prime factor decomposition of the DFT and the DHT/discrete cas-cas transform (DCCT), respectively. The method of Rader is employed to convert the subspace DFT/DHT modules into cyclic convolutions (CCs). These are further dissected into CCs and skew-cyclic convolutions (SCCs), respectively, of length ½(Ni− 1), whereNiis the DFT/DHT module length in the ith stage. That allows both real and complex DFT modules, as well as DHT modules, to be computed with the same convolver structure, by a simple reconfiguration of a recombination stage.This has important consequences for hardware implementations as only one type of convolver needs to be fabricated. A family of VLSI building block processors (BBPs) with pipelined bit-serial arithmetic is proposed. All inner products are computed in parallel within each BBP, resulting in a throughput rate inversely proportional to ½(Ni+ 1). This leads to easy load balancing, which is discussed first in the context of a array machine and then in that of a multiplexed pipelined machine.
DOI:10.1049/ip-g-2.1990.0059
出版商:IEE
年代:1990
数据来源: IET
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9. |
Electrical characterisation of the insulating property of Ta2O5in AI–Ta2O5–SiO2–Si capacitors by a low-frequencyC/Vtechnique |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 5,
1990,
Page 390-389
J.-G.Hwu,
S.-T.Lin,
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摘要:
The measurement of equivalent low-frequency capacitance is used as an efficient method to monitor the insulating properties of Ta2O5in Al–Ta2O5–SiO2–Si (MTOS) structures. It is found however, that MTOS devices having normal high-frequencyC/Vcharacteristics can have significantly different behaviour at low frequencies. A technique is proposed in this work that enables the quality of the Ta2O5preparation to be determined. Examples showing the importance of the measurement of the equivalent lowfrequency capacitance are also given.
DOI:10.1049/ip-g-2.1990.0060
出版商:IEE
年代:1990
数据来源: IET
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10. |
Analytical determination of output resistance and DC matching errors in MOS current mirrors |
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IEE Proceedings G (Circuits, Devices and Systems),
Volume 137,
Issue 5,
1990,
Page 397-404
Z.Wang,
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摘要:
A new technique for the analytical determination of output resistance and current ratio or DC matching errors in MOS current mirrors is presented, emphasising, in comparison four types of frequently used circuit: the simple current mirror, the Wilson current mirror, the improved Wilson current mirror and the cascode current mirror. Formulas that precisely describe the performance parameters are derived. The minimum output voltage is also discussed. A review of other types of current mirror configurations is included.
DOI:10.1049/ip-g-2.1990.0061
出版商:IEE
年代:1990
数据来源: IET
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