摘要:

To solve linear state equations, a two-dimensional systolic-array system has been proposed. For the same purpose, various kinds of one-dimensional arrays are designed in the paper. The linear systolic-array system with first-in-first-out (FIFO) queues can be designed by applying double projections from the three-dimensional dependence graph (DG). As the array thus designed needs processors with multifunction operations and various input/output requirements, tag control bits are incorporated, and so make the overall computation more efficient. Furthermore, a linear systolic-array system with content addressable memory (CAM) is designed which can use the advantage of matrix sparseness to reduce the overall computation time. The partition scheme of the linear systolic-array system is also proposed to match the limitation of the pin number and the chip area. Finally, the cost and performance of all the class of systolic-array systems for solving linear state equations are illustrated.

DOI:10.1049/ip-g-2.1990.0028

出版商:IEE    

年代:1990

数据来源: IET

摘要:

A new high-frequency high-efficiency resonant DC/DC convertor is introduced. It is composed of a Class E inverter and a Class E rectifier. The convertor operates with load resistances ranging from a full load to infinity. It can regulate the output voltage by varying the switching frequency over a narrow range, owing to a high value of the loaded quality factorQL(≥5). The measured relative bandwidth was δf/fmin= 14.39% as the load resistance was increased from 20 ω to an open circuit. Zero-voltage switching was maintained for both the controlled switch and the rectifier diode over the entire load range. The output voltage was varied from 10 to 30 V at an input voltage of 20 V. The measured DC/DC conversion efficiency was 80.3%.

DOI:10.1049/ip-g-2.1990.0029

出版商:IEE    

年代:1990

数据来源: IET

摘要:

The dream of a direct electronic analogue for a biological nose may still be some way from realisation, but considerable progress can be reported towards prototype computerised instruments capable of equivalent, or even better, performance in certain applications. The achievements are partly attributable to success in new circuit and systems approaches, as well as in developing sensing devices, with the prospect of further rapid progress based on the exploitation of materials and integrated sensor technology. Other important advances are being created in information processing, particularly in relation to pattern recognition.

DOI:10.1049/ip-g-2.1990.0030

出版商:IEE    

年代:1990

数据来源: IET

摘要:

An orthogonal series approach is presented for state-space analysis of 1-D and 2-D linear time-invariant discrete systems. This approach makes use of the backward shift operation matrix derived in the paper, and yields explicit expressions for the state and output orthogonal coefficient matrixes. These expressions involve only multiplication of small dimension matrixes thus simplifying the computational effort as compared to known orthogonal function techniques, where the inversion of large matrixes is required.

DOI:10.1049/ip-g-2.1990.0031

出版商:IEE    

年代:1990

数据来源: IET

摘要:

The macrocell approach to the design of VLSI integrated circuits needs a tool for the solution of the switchbox problem, where terminals lie on all the edges of a generic rectilinear region. In the paper, such a problem is thoroughly analysed and a two-layer symbolic router is proposed, which is able to successfully route very dense examples of switchboxes. The program applies a suitable algorithm which tries to connect nets like an expert designer. Connections are placed without affecting the wireability of further connections, when this is possible. In crowded situations, blocking nets are identified and other solutions are tried by a rip-up and rerouting step. In this way, it is possible to notably extend the space in which to search for a solution.

DOI:10.1049/ip-g-2.1990.0032

出版商:IEE    

年代:1990

数据来源: IET

摘要:

A novel three terminal GaAsn+-i-p+-i-n+negative differential resistance device prepared by molecular beam epitaxy is demonstrated for the first time. The peak-to-valley current ratios can be modulated by the third external applied voltage which can be expressed asIp/Iv= 5.08 × 10−3exp [1.999VBE] at room temperature, whereVBEis in units of volts. It implies that large peak-to-valley current ratios (e.g.IP/Iv= 300 atVBE= 5.5 V) and large peak current densities can easily be obtained just by increasing theVBEbias. A phenomenological bipolar-unipolar transition model is proposed to interpret the observed behavior and confirmed by experiments.

DOI:10.1049/ip-g-2.1990.0033

出版商:IEE    

年代:1990

数据来源: IET

摘要:

A new logic element, My-box, is proposed to model the line faults (stuck-at-1 and stuck-at-0) and the transistor faults (stuck-on and stuck-open) of CMOS circuits, which consist of fully CMOS logic, pseudonMOS logic, dynamic CMOS logic, clocked CMOS (C2MOS) logic, CMOS domino logic and NORA CMOS logic. It can also be used to model the faults and the functions of a transmission gate logic. A procedure is described to transform a transistor level CMOS circuit to a gate-level equivalent circuit which is composed of AND, OR and the My-box logic element. A fault collapsing procedure is also derived to determine the representative set of prime faults (RSPF) for the transformed gate-level circuit. By applying this procedure to ten benchmark circuits, the number of faults can be reduced to approximately 15% of the original total faults, if the ten benchmark circuits are implemented in the fully CMOS logic.

DOI:10.1049/ip-g-2.1990.0034

出版商:IEE    

年代:1990

数据来源: IET