摘要:

Fault tolerant design is receiving considerable attention at present in order to safeguard against improper operation of digital systems in critical applications. A number of multiprocessor systems featuring hardware fault tolerance are now available commercially. The paper presents an overview of some of the work done so far in the application of fault tolerance techniques to improve the reliability and availability of microprocessor-based systems. An alternative approach to enhance the reliability of a system is to apply self-checking techniques, primarily through the use of error detecting codes. By merging the fault tolerance and the self-checking techniques, the reliability and the maintainability of microprocessor-based systems can be significantly improved.

DOI:10.1049/sm.1985.0015

出版商:IEE    

年代:1985

数据来源: IET

摘要:

A design approach is presented for a general-purpose VLSI fault tolerant microprocessor, with redundancy designed into the internal chip architecture. The design features are internal automatic state storage and rollback/retry mechanism and a microprogrammed ALU design. The reliability of the design is estimated using a system model of reliability behaviour, and is compared with that of other fault tolerant design strategies. Finally, the effect of the fault tolerance on processor performance is discussed.

DOI:10.1049/sm.1985.0016

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The fault tolerant approach to building reliable systems acknowledges that perfection is impossible (or at best very expensive) and therefore tries to cope with the consequences of residual defects within the system. Fault tolerance has an established role in detecting and masking component faults in hardware systems, but has also been advocated as a defence against deficiencies of design. The paper argues, in question and answer format, the case for adopting design fault tolerance techniques in practical systems.

DOI:10.1049/sm.1985.0017

出版商:IEE    

年代:1985

数据来源: IET

摘要:

Transient disturbances to microprocessor systems can cause program execution to depart from its normal sequence of operations. In the paper figures for the probability of recovery following a transient disturbance are calculated. The approach is based on analysis of program execution following a random jump to an arbitrary address within the memory map, and comparative figures are presented for a number of microprocessors. Suggestions are made for enhancing the probability of recovery.

DOI:10.1049/sm.1985.0018

出版商:IEE    

年代:1985

数据来源: IET

摘要:

The paper discusses ways of building a dual processed computer system to provide a highly reliable fault tolerant configuration. The need and justification for fault tolerant systems is discussed and the comparative availability that can be expected from single and dual configurations is calculated. Based on systems implemented by CAP, two of the most important types of dual processing systems are discussed: namely load sharing and continuous processing systems. The load sharing approach to fault tolerance is particularly important for transaction processing applications because it offers the opportunity to build a fault tolerant system for a cost close to that of a conventional single-computer system. An example based on CAP's system for the Durham Constabulary on Perkin-Elmer equipment is discussed. The continuous processing system described is based on CAPTEC, CAFs operating system for Digital Equipment Corporation computers, which provides a continuous processing system where the system continues uninterrupted on a single failure.

DOI:10.1049/sm.1985.0019

出版商:IEE    

年代:1985

数据来源: IET