摘要:

We have identified a first‐wafer effect for photoresist ashing and silicon nitride‐polysilicon stripping in remote plasma reactors. The first‐wafer effect consists of the first wafer etching differently from the subsequent wafers in a lot. For photoresist ashing, the first wafer ashes faster than subsequent wafers. For silicon nitride and polysilicon stripping, first wafers show higher etch rates of silicon nitride and polysilicon, while silicon dioxide first wafers etch faster for the polysilicon strip process, and slower for the silicon nitride strip process. We have modeled the first‐wafer effect for photoresist ashing. We found an inverse relationship between the percentage change in the time to clear the photoresist from the wafer and the time delay between processing sequential wafers. We have included this first‐wafer effect in the on‐line statistical process control strategy for the photoresist asher in our laboratory. Examination of this first‐wafer effect suggests that it may be caused by the generation of species in the discharge in the first few seconds of operation that alter the reactivity of the chamber walls. While these species are quick to adsorb on the walls, they only desorb slowly. Pumping on the chamber in the absence of a microwave discharge returns the chamber to its original state.

ISSN:1071-1023    

DOI:10.1116/1.587196

出版商:American Vacuum Society    

年代:1994

数据来源: AIP

摘要:

Stresses which build up in thin films such as tantalum, during thermal processing, can cause major reliability problems in electronic and x‐ray optics applications. We demonstrate that 50–200 nm thick sputtered β‐Ta thin films undergo repeated compressive stress increases when thermally cycled to 400 °C (at a rate of 10 °C/min) and back in a purified He ambient because of small amounts of oxygen gettered by the tantalum. The oxygen contamination results from the poor quality of the atmospheric seal on the quartz annealing chamber. As‐deposited Ta thin films have a compressive stress ranging from −1 to −4 GPa. The compressive stress buildup was monitoredinsituand was shown to increase −0.5 GPa on average after each thermal cycle for a final value from −6 to −7 GPa after seven cycles. After being cycled thermally seven times any perturbation of the film such as a four‐point probe resistivity measurement can cause the film to instantaneously crack in a serpentine pattern, relieving the large compressive stress. Auger electron spectroscopy depth profiling analysis was used to determine that the as‐deposited film contained 1 at. % oxygen which increased to 8%–12% after seven thermal cycles with an approximate doubling in resistivity. The −0.5 GPa average compressive stress increase in Ta thin films when cycled to 400 °C is attributed to a 1.3% increase in oxygen concentration leading to a Ta unit cell expansion of 0.6%.

ISSN:1071-1023    

DOI:10.1116/1.587197

出版商:American Vacuum Society    

年代:1994

数据来源: AIP

摘要:

Capacitors made up of thin films of Ta2O5/TiN on polysilicon have been studied for application to 256 Mbytes dynamic random access memories. In this study, the thermal stability of poly‐Si/Ta2O5films with TiN electrode film deposited by (i) chemical vapor deposition (CVD) with TiCl4and NH3, (ii) sputtering, and (iii) metalorganic CVD (MOCVD) was compared. These samples were annealed under vacuum at 700, 800, and 900 °C for 30 min. The as‐deposited and the annealed samples were analyzed by Rutherford backscattering with 2 MeV He+ions. The CVD TiN films, which contained a small amount of Cl, provided pathways for the underlying Ta2O5to out‐diffuse during annealing at all temperatures between 700 and 900 °C. The sputtered films were resistant to the diffusion of Ta2O5up to 800 °C, but relented at 900 °C, with measurable outdiffusion of Ta. There was no noticeable interaction of the Ta2O5with the TiN layers, deposited by the MOCVD process, at temperatures up to 900 °C. However, the MOCVD TiN films were found to contain light elements such as carbon and oxygen, which were slightly reduced on annealing. Nuclear reaction analysis and secondary ion mass spectroscopy were used to detect the concentrations and depth profiles of light elements. These indicate presence of C and O contents up to at least 20 at. % in these films.

ISSN:1071-1023    

DOI:10.1116/1.587198

出版商:American Vacuum Society    

年代:1994

数据来源: AIP

摘要:

Planarization of aluminum films has been achieved by using the combination of molecular beam deposition (MBD) and annealing for ultralarge‐scale integration metallization. The resulting via holes for multilevel interconnection in the metallization are found to be filled by a plug of aluminum. This MBD is an effective deposition method for producing a desired aluminum film; the aluminum is fully deposited on the sidewall and bottom of vias without an overhang occurring. This desired aluminum film is realized because the direction of incoming aluminum vapor is controlled. The direction control is performed with an angle definition and scattering prevention of the vapor. A mass transport of aluminum is created during this annealing procedure. This desired aluminum film is needed in order to perform the via filling and planarization because the mass transport is attributed to the surface tension forces generated by the three‐dimensional geometry of the heated aluminum. The resulting condition includes an undesired void in via hole if the aluminum is not fully deposited on the sidewall and bottom of vias. This technique has been shown to allow excellent via filling with the annealing at low temperature (300 °C), and is applicable to filling submicrometer‐diameter vias having a diameter of 0.58 μm with a 1.1‐μm depth (aspect ratio ∼1.9). The resulting surface of aluminum films is planarized.

ISSN:1071-1023    

DOI:10.1116/1.587199

出版商:American Vacuum Society    

年代:1994

数据来源: AIP

摘要:

Recently it has become common to use dry vacuum pumps in semiconductor manufacturing processes. One problem with this application, however, is that etching by‐products (e.g., aluminum trichloride, AlCl3) often deposit in the pumps. We have therefore studied these deposition processes and techniques to prevent deposits from forming. Our results indicate that the gas passage temperature must be kept above the sublimation temperature of the substance passing through the pump (e.g., AlCl3) to prevent deposits from forming. To accomplish this, we modified the cooling jacket construction and changed the coolant from water to oil. The modified cooling jacket resulted in more uniform temperatures than with the previous cooling jacket. Considering AlCl3, the gas passage temperature was raised by about 50 °C in order to keep the gas above the sublimation temperature of AlCl3. The modified pump was operated with a test semiconductor apparatus. A small amount of deposit was found after one year of equivalent running time, but it was not enough to interfere with proper operation of the pump. The same pump was also successfully demonstrated with a silicon nitride chemical vapor deposition process.

ISSN:1071-1023    

DOI:10.1116/1.587200

出版商:American Vacuum Society    

年代:1994

数据来源: AIP

摘要:

As device densities in integrated circuits have grown, the number of connections between them has followed, resulting in larger chips with increased numbers of layers of metal wiring. Traditionally these layers of wiring were fabricated using aluminum and its alloys for the conductor and silicon oxide as the dielectric and insulator. New combinations of dielectrics and metals promise improved performance and increased reliability, which can require alternative methods of fabrication.

ISSN:1071-1023    

DOI:10.1116/1.587201

出版商:American Vacuum Society    

年代:1994

数据来源: AIP

摘要:

Formation of Si–SiO2stacked‐gate heterostructures requires (i) preparation of Si surfaces prior to interface formation and oxide deposition, (ii) oxide deposition, (iii) polysilicon gate electrode deposition, and generally (iv) post‐deposition doping of the gate electrode. Mid‐ and/or end‐process rapid thermal annealing performed in inert or oxidizing ambients may also be necessary to optimize device performance.Fourphasesin the development of an integrated processing protocol for stacked‐gate structures are described in which these steps have been modified, and continuously improved. Process tools have evolved from (i)single‐functionchambers for (a) surface cleaning/passivation, and (b) thin film deposition, to (ii)dual‐function/singleprocessplasma chambers for (a)in‐situsurface cleaning and interface formation and (b) oxide deposition, and finally to (iii)multi‐function/dualprocesschambers in which all of the above process steps are doneinsitu, but by more than one processing technique. This last approach has culminated in chambers which can accommodate (i)low‐temperatureplasma‐assisted interface formation at ∼300 °C, (ii)intermediate‐temperaturerapid thermal dielectric and polysilicon depositions at 600–800 °C, and (iii)higher‐temperaturerapid thermal annealing at 900–1000 °C.

ISSN:1071-1023    

DOI:10.1116/1.587202

出版商:American Vacuum Society    

年代:1994

数据来源: AIP

摘要:

Chemically assisted ion beam etching (CAIBE) and electron cyclotron resonance (ECR) plasma deposition have been used to etch and coat 1.3 μm InGaAsP/InP heterostructure lasers in full wafer form. Ar/Cl2CAIBE, using an ECR dual grid ion source, was used to etch 4 μm deep vertical (90°±0.5°), smooth facets at rates up to 1.3 μm/min. An integrated back facet monitor was simultaneously fabricated in the same heterostructure. High‐reflectivity Si/SiO2optical coatings were deposited on the etched facets by low‐temperature (<120 °C) ECR plasma deposition and selectively patterned by liftoff. Full wafer testing of the processed devices showed good uniformity (±3%) with laser threshold currents of 25 mA and a slope efficiency of 0.23 W/A at 25 °C and 0.11 W/A at 85 °C. Back facet monitor efficiency was 0.4 A/W over the whole temperature range.

ISSN:1071-1023    

DOI:10.1116/1.587203

出版商:American Vacuum Society    

年代:1994

数据来源: AIP

摘要:

The ADEQUAT project [Advanced Developments for Quarter Micron complementary metal–oxide–semiconductor (CMOS) Technologies] is executed by a European consortium under the JESSI/ESPRIT programs. It aims at developing new device structures and process modules for the 0.35 and 0.25 μm CMOS logic technology generations, offering improved performance while meeting the reliability and manufacturability constraints. Several examples of choices illustrating this optimization process are presented together with the overall project organization and roadmap.

ISSN:1071-1023    

DOI:10.1116/1.587204

出版商:American Vacuum Society    

年代:1994

数据来源: AIP

摘要:

During the course of the Microelectronics Manufacturing Science and Technology (MMST) program, a number of sensors have been integrated into various test‐bed plasma etch reactors with the goal of monitoring, diagnosing, and controlling these processes. These sensors include single wavelength and spectral ellipsometers for real‐timeinsituetch rate and endpoint determination; a standard monochromator for etch rate and nonuniformity measurements; an eddy current sensor for incoming metal thickness control; a rf monitor for rf current and voltage diagnostics; and a scatterometry‐based critical dimension sensor for linewidth measurements. The full integration of these sensors turned out to be a complex and time‐consuming task including hardware, optical, software, material, and processing issues. Once integrated into the reactor, and the appropriate process modeling completed, these sensors enabled the monitoring, diagnosis, and model‐based control of these processes. Besides maintaining specific process observables at their target values, running under process control has highlighted phenomena such as equipment aging and first‐wafer effects. This work has clearly shown that the full implementation of sensors into commercial manufacturing equipment is essential for the model‐based control and diagnosis of semiconductor processes.

ISSN:1071-1023    

DOI:10.1116/1.587205

出版商:American Vacuum Society    

年代:1994

数据来源: AIP