摘要:

The emergence of the electronic beam squint (EBS) satellite-tracking technique offers the possibility of low-cost, high-performance systems suitable for earth station, maritime and satellite terminals. Initial work done by the originating researchers laid the foundations for future development and demonstrated the considerable potential of the technique. Work now being undertaken aims to further current knowledge significantly by examining a number of key areas, including feed design, application of control algorithms and receiver technology. As part of this exercise, the development of a software model of a complete EBS system has been undertaken. The simulation package provides a realistic environment in which differing system configurations and operational situations have been investigated. Modelling of perturbing effects, such as polarisation rotation, mechanical misalignment and atmospheric disturbances has, for the first time, provided concise data on operational performance under these conditions. The paper, following an introduction to the EBS scheme, describes the model and software package developed, presents initial results, and analyses the implications for future implementation strategies.

DOI:10.1049/ip-i-2.1989.0025

出版商:IEE    

年代:1989

数据来源: IET

摘要:

The main properties of a network topology based on the Cartesian product of two complete graphs are briefly reviewed and the problems involved in the application of this type of structure to a multiexchange network are analysed. An approximate solution to the problem of assigning nodes of the network to exchanges (whose traffic matrix is known) is presented. This is obtained from a heuristic algorithm which involves solving a number of linear programming problems. Finally, a computational method for modelling a multiexchange digital network is applied to a network of very high traffic capacity such as might be the case for the top level of a digital national telecommunications network.

DOI:10.1049/ip-i-2.1989.0027

出版商:IEE    

年代:1989

数据来源: IET

摘要:

A new explanation of the Berlekamp-Massey algorithm is given using a method that is not based on the usual description as shift register synthesis but in terms of matrices. It has the advantage of being more didactic and it reveals some properties that cannot be deduced so easily from Massey's interpretation.

DOI:10.1049/ip-i-2.1989.0028

出版商:IEE    

年代:1989

数据来源: IET

摘要:

A multicarrier demodulator (MCD) suitable for advanced digital satellite communications is presented. This system permits the direct interfacing of FDMA and TDM communication links by using digital signal processing techniques. Two main functions are implemented by an MCD: demultiplexing and demodulation. We focus here only on a digital implementation of an MCD with a view to achieving flexibility, better performance and suitability for VLSI.The demultiplexer is implemented according to a per-channel structure based on an analytic signal method that allows a highly modular and flexible implementation to be achieved. This approach permits a certain degree of integration of the demultiplexer and demodulator functions. In the proposed MCD scheme the receiver pulse-shaping filter can be integrated in the demultiplexer structure, thus lowering the overall implementation complexity. Coherent demodulation is used to reduce the signal-to-noise ratio required to achieve a specified bit error rate and is carried out using the maximum likelihood (ML) estimation method. A maximuma posterioriprobability (MAP) method is used to jointly estimate the carrier phase and bit timing of the received signal. The digital architecture of the proposed MCD can be adapted to different digital modulation techniques. However, we focus here on the application for QPSK signals, since this modulation scheme is of interest in digital satellite communications. A theoretical analysis and computer simulations are performed in order to evaluate the performance degradation of the proposed MCD, including the finite arithmetic implementation.

DOI:10.1049/ip-i-2.1989.0029

出版商:IEE    

年代:1989

数据来源: IET

摘要:

A new digital implementation of a receiver for digital communications is presented. The receiver structure performs the integration of a maximuma posterioriprobability (MAP) carrier and clock synchronisation with the maximum likelihood (ML) demodulation. It is shown that the key feature of the receiver structure is that the same hardware is able to perform both operations; thus the receiver implementation complexity is greatly reduced. This scheme can be adapted to different modulation techniques suitable for digital communications, such as QPSK, O-QPSK and MSK. As examples, the application to QPSK and MSK signals is considered, owing to the interest of these modulation schemes for satellite communications.

DOI:10.1049/ip-i-2.1989.0030

出版商:IEE    

年代:1989

数据来源: IET

摘要:

The application of concatenated coding to increase throughput in automatic repeat request (ARQ) protocols is described. In the proposed schemes, which are implemented with an inner error detection-correction code and an outer error-detection code, the inner code's dualfunction structure significantly enhances ARQ efficiency, especially in cases of high communication channel error rate. Results of a comparative analysis show that the proposed schemes outperform other similar ARQ protocols.

DOI:10.1049/ip-i-2.1989.0031

出版商:IEE    

年代:1989

数据来源: IET

摘要:

The paper gives throughput results in terms of capacities per unit bandwidth for a multiaccess spread-spectrum communication system with a large number of users. Various spread-spectrum schemes are included. The direct sequence scheme with a sine pulse as the chip pulse gives the maximum throughput of log2e(= 1.44) bit/Hz. The frequency hopping schemes withM-ary frequency-shift keying have the smallest throughput; assuming detection with side information, forM= 2 the throughput is equal to that of slotted ALOHA (e−1) and decreases asMincreases.

DOI:10.1049/ip-i-2.1989.0032

出版商:IEE    

年代:1989

数据来源: IET

摘要:

The paper presents a new hardware decoder for double-error-correcting binary BCH codes of primitive length, based on a modified step-by-step decoding algorithm. This decoding algorithm can be easily implemented with VLSI circuits. As the clock rate of the decoder is independent of block length and is only twice the data rate, the decoder is suitable for long block codes working at high data rates. The decoder comprises a syndrome calculation circuit, a comparison circuit and a decision circuit, which can be realised by linear feedback shift registers, ROMs and logical gates. The decoding algorithm, circuit design and data processing sequence are described in detail. The circuit complexity, decoding speed and data rate of the new decoder are also discussed and compared with other decoding methods.

DOI:10.1049/ip-i-2.1989.0033

出版商:IEE    

年代:1989

数据来源: IET