摘要:

The author describes IEE activities relevant to the computing industry, particularly those of the Computing and Control Division, and looks at ways in which some of these might be extended to show benefit to both IEE members and the computing industry in general. Of specific significance are the recent activities in the area of standards and guidelines, where the Division has now five working parties engaged in a variety of different tasks of relevance to the computing industry.

DOI:10.1049/ip-e.1986.0001

出版商:IEE    

年代:1986

数据来源: IET

摘要:

The paper reviews the evolution of semiconductor memories from the early 1960s to the present day. It includes descriptions and comparisons of the principal types of memory presently available, followed by a survey of the main semiconductor technologies used in the fabrication of VLSI memories. Typical cell designs are first presented, starting with basic electrical designs and proceeding to show how these may be implemented as layouts for a practical chip. The fabrication steps required to realise such cells within a memory chip are described. The design and organisation of complete memories is then discussed; the design of the principal types of read-only memories, read/write memories, content-addressable memories and serial memories being included. The remainder of the paper deals with the important topic of specification and timing requirements of memories; followed by a general review of different types of semiconductor memory, both from the applications point of view and as a comparison of their principal characteristics with those using alternative fabrication technologies. Finally, there is brief projection of future developments. The paper is written throughout primarily from the technological rather than the applications viewpoint.

DOI:10.1049/ip-e.1986.0002

出版商:IEE    

年代:1986

数据来源: IET

摘要:

In the paper we develop an approach to fault diagnosis in combinational circuits yielding a new method based on an effect-cause analysis. In our method the circuit under test N*is studied by using a description of its behaviour called the operation map. Depending on the set of tests applied, this description may allow the fault in N*to be detected before, and independently of, being located. The elimination of inputs in the operation map allows us to find the fault situations in N*(causes) which are compatible with the applied test and the obtained response (the effect). The method presented does not require a fault dictionary, fault enumeration or knowledge of the values expected in the fault-free circuit, and it makes possible applications such as obtaining faults not detected by a given test (including redundant faults), the identification of faults which cannot be modelled as stuck-at faults and other applications characteristic of this type of analysis.

DOI:10.1049/ip-e.1986.0003

出版商:IEE    

年代:1986

数据来源: IET

摘要:

The paper presents a new iterative array, which performs the triangularisation of a dense matrix, using the Givens rotation algorithm. Two slightly different arrays are presented: the first performs the factorisation of a single matrix; the second performs the recursive triangularisation. Partitioning of the first structure is also considered, in order to cope with matrices larger than the array. The implementation of the cell in the array is based on on-line arithmetic, which allows us to obtain high performances. Furthermore, the cell implementation requires only three types of arithmetic units (multiplication/addition, square root, division) and shift registers for data buffering and for generating the timing signals.

DOI:10.1049/ip-e.1986.0004

出版商:IEE    

年代:1986

数据来源: IET

摘要:

A procedure for determining synchronisation status for a T-code decoder is developed from material presented in an earlier work. A general form for a probability-transition matrix description of the T-code synchronisation process is deduced leading to a proof in which the T-codes are shown to be statistically synchronisable. By evaluating the transition probabilities for an elementary example, numerical techniques for determining the synchronisation probabilities distribution (SPD) and the expected synchronisation delay (ESD) are illustrated. Further evaluation of the ESD for a series of eleven minimal augmented binary code sets suggests asymptotic logarithmic growth of the ESD as a function of set augmentation. Practical aspects for determining decoder synchronisation status are discussed with particular reference to the elementary example introduced in the early part of the paper.

DOI:10.1049/ip-e.1986.0005

出版商:IEE    

年代:1986

数据来源: IET

摘要:

Many approaches have been developed for designing large, highly parallel computer systems. Classical synchronous approaches are susceptible to synchronisation problems at the clock pulse level. Newer asynchronous approaches, on the other hand, avoid such problems but are expensive to implement. This paper proposes a compromise approach that builds on the well developed synchronous system design techniques and, at the same time, avoids the clock pulse level synchronisation problems. In this approach, a system has a totally synchronous core with a 'stoppable' clock and uses an asynchronous interface for external communication. With the clock not running, the asynchronous interface receives and sends information in the form of packets, setting up the proper input values and initial state for the synchronous core. The clock is then started, and the synchronous core behaves as a sequential state machine initialised to the proper state and subjected to the proper input values. When the core has finished its computation, the clock is stopped and the process is repeated. A methodology for building such systems is presented in the paper.

DOI:10.1049/ip-e.1986.0006

出版商:IEE    

年代:1986

数据来源: IET