摘要:

MOS VLSI circuits are often tested by using the stuck-at fault model to generate and evaluate test sequences that are intended to distinguish faulty from fault-free circuits. However, MOS circuits exhibit a wide variety of failure modes and there is no guarantee that the model accurately reflects the ways in which they fail. The paper gives many examples of faults taken from faulty NMOS circuits and discusses their associated fault-effects on a typical NMOS structure. It describes a series of experiments in which test patterns derived using different fault models are used to test 529 NMOS multiplexers. 12% of the chips tested and identified as being fault-free by a test set derived using the stuck-at fault model were faulty. In addition, two functional-level test sequences made up of identical test vectors arranged in different order were used to test the multiplexers. One correctly identified all the faulty circuits; the other identified 9% of the faulty circuits as being fault-free. The paper concludes that the stuck-at model is inadequate for testing MOS circuits, because of its use of a gate-level representation of the circuit under test. A more accurate method for generating and evaluating MOS circuit test patterns is to work from the switchlevel representation of the circuit under test, testing for transistor stuck-on and stuck-open faults.

DOI:10.1049/ip-e.1988.0001

出版商:IEE    

年代:1988

数据来源: IET

摘要:

CMOS circuits present some unique testing problems. Certain physical failures are not adequately represented by the traditional stuck-at fault model. Opens in transistors or their connections, a ‘stuck-open’ fault, can require a sequence of tests. A number of test schemes employing exhaustive or pseudo-exhaustive input sequences have appeared in the literature. Here we examine the applicability of such a method to the testing of stuck-open faults in CMOS combinational circuits. It is shown that without careful planning an exhaustive test may not detect all stuck-open faults. A universal input sequence which will detect all stuck-open faults is proposed. This sequence corresponds to a Eulerian cycle in a directed hypercube. A circuit which generates such a sequence is outlined.

DOI:10.1049/ip-e.1988.0002

出版商:IEE    

年代:1988

数据来源: IET

摘要:

Cryptographic binary sequence generators are discussed in which a linear feedback shift register is clock controlled in a pseudorandom manner by another register. Huge values of the linear equivalence are readily achieved. To illustrate the possibilities three types of generator are described: First, the output from a clockcontrolled shift register is scrambled by a MacLaren-Marsaglia shuffler. Secondly, the output sequence is generated as the scalar product of the state-vector of a clock-controlled shift register with a pseudorandom sequence of vectors and thirdly, a cascade of clock-controlled shift registers is set up in which several bits are passed in parallel from stage to stage through invertibles-boxes. A new version of the theorem which guarantees large values of the linear equivalence is given, together with a proof along novel lines.

DOI:10.1049/ip-e.1988.0003

出版商:IEE    

年代:1988

数据来源: IET

摘要:

The design of a new, fast systolic stack is systematically carried out by traversing the qualitatively distinct levels of representation of the VLSI design hierarchy. Included in the overall VLSI design process is a formal verification of design correctness, circuit design and layout, as well as a performance analysis of area, time, clock frequency and design extendability. The novel systolic network has been obtained from a known network by applying a transformation technique based on packing and unpacking data elements intopackets; the packet approach is used as a timing optimisation technique to eliminate the slowness of the known network.

DOI:10.1049/ip-e.1988.0004

出版商:IEE    

年代:1988

数据来源: IET

摘要:

A case study is presented which involves the implementation of the discrete cosine transform; a commonly encountered algorithm in image data compression coding. Two commercially available digital signal processing devices are considered. The use of a more highly integrated component, despite offering the potential for greater processing power, does not necessarily result in the most suitable solution. This is because the internal architecture of the component imposes a particular structure on a solution, which can lead to extra complexities if this structure does not closely match that of the algorithm. In addition, it is shown that manipulation of the basic algorithm to suit the hardware is an important consideration when designing for real time solution.

DOI:10.1049/ip-e.1988.0005

出版商:IEE    

年代:1988

数据来源: IET

摘要:

A new approach to corner detection is described which is based on the generalised Hough transform. The approach has the advantage that it can be used when objects have curved sides or blunt corners, as frequently happens with food products; in addition, it can be tuned for varying degrees of corner bluntness. The method is inherently sensitive: we have shown how it may be optimised for accuracy in the measurement of object dimensions and orientation.

DOI:10.1049/ip-e.1988.0006

出版商:IEE    

年代:1988

数据来源: IET

摘要:

The Fano algorithm for sequential decoding permits the simultaneous comparison of a serial bit pattern with a large number of reference patterns, and is applicable to the identification of addresses in local area networks. Such a requirement arises frequently in the design of bridges (filtered, buffered, repeaters) between networks, operating at the data link layer so as to be transparent to various higher-level protocols. The paper explains how the algorithm functions and how it can be implemented in hardware, operating in real time as the address bits arrive. Several specific applications are discussed.

DOI:10.1049/ip-e.1988.0007

出版商:IEE    

年代:1988

数据来源: IET

摘要:

We consider the problem of producing all the roots of a polynomialp(x) =a0xn+a1xn−l+ … +an(where all the roots are distinct) by an iterative systolic array. Two basic arrays are considered, one where the position of the roots remain stationary and another where they are non-stationary. The former scheme requiresO(n) basic cells, the latterO(z) cells withz(>0) a suitably chosen constant determining the number of root approximations on a single pass through the array. Finally an area efficient systolic ring is discussed requiringO(n/A) cells to compute an arbitrary number of root approximations.

DOI:10.1049/ip-e.1988.0008

出版商:IEE    

年代:1988

数据来源: IET

摘要:

A modification of Rueppel's concept of self-decimating sequences enables the design of binary self-clocked linear feedback shift registers of prime period. These in turn may be used as stages in Gollmann's cascade of clock-controlled registers to produce sequences with linear equivalence and period comparable to an upper bound determined by the total number of storage elements.

DOI:10.1049/ip-e.1988.0009

出版商:IEE    

年代:1988

数据来源: IET

摘要:

Two systolic arrays for the VLSI implementation of the decimation and interpolating structures advanced by Valenzuela and Constantinides are presented. Each of the resultant arrays consists of basic cells characterised by nearest neighbour interconnections and high throughput rate.

DOI:10.1049/ip-e.1988.0010

出版商:IEE    

年代:1988

数据来源: IET