摘要:

John Bardeen and Walter Brattain invented the point-contact semiconductor amplifier (transistor action) in polycrystalline germanium (also observed in polycrystalline silicon) on Dec. 15, 1947, for which they received a patent on Oct. 3, 1950. Bill Shockley was not a co-patent holder on Bardeen and Brattain’s point-contact semiconductor amplifier patent since Julius Lilienfeld had already received a patent in 1930 for what would have been Shockley’s contribution; namely, the field-effect methodology. Shockley received patents for both his minority-carrier injection concept and junction transistor theory, however, and deservedly shared the Nobel prize with Bardeen and Brattain for his seminal contributions of injection, p-n junction theory and junction transistor theory. We will review the events leading up to the invention of Bardeen and Brattain’s point-contact semiconductor amplifier during the magic month of November 17–December 16, 1947 and the invention of Shockley’s junction semiconductor amplifier during his magic month of December 24, 1947–January 23, 1948. It was during the course of Bardeen and Brattain’s research in November, 1947 that Bardeen also patented the essence of the MOS transistor, wherein the induced minority carriers were confined to the inversion layer enroute to the collector. C. T. Sah has described this device as a sourceless MOS transistor. Indeed, John Bardeen, co-inventor of the point-contact semiconductor amplifier and inventor of the MOS transistor, may rightly be called thefatherof modern electronics. ©2001 American Institute of Physics.

ISSN:0094-243X    

DOI:10.1063/1.1354371

出版商:AIP    

年代:1901

数据来源: AIP

摘要:

In the PC Era, Microcomputer (&mgr;C) and memory were the components that drove growth of the PC industry. In the Internet Era, Digital Signal Processing (DSP) and Analog will be the components that drive growth in Internet Products. Over the next 10 years, technology will continue to follow Moore’s Law of scaling, and in addition System-on-a-Chip (SOC) integration will drive technology. ©2001 American Institute of Physics.

ISSN:0094-243X    

DOI:10.1063/1.1354372

出版商:AIP    

年代:1901

数据来源: AIP

摘要:

The aggressively shrinking process window drives the semiconductor manufacturer to examine, refine, and control all aspects of the manufacturing process. Process budgets leave little room for error contribution. Budget management, and ultimately achieving the goal, requires an understanding of the constituent components, and development of mitigation strategies. We present some of the challenges facing our industry and strategies that we are taking to address them. ©2001 American Institute of Physics.

ISSN:0094-243X    

DOI:10.1063/1.1354373

出版商:AIP    

年代:1901

数据来源: AIP

摘要:

The International Technology Roadmap for Semiconductors (ITRS) provides the semiconductor industry with the timing of critical technology needs for future generations of integrated circuits. The Metrology roadmap in the ITRS describes the measurement needs based on the process requirements found in the Lithography, Front End Processes, Interconnect, and Packaging Roadmaps. This paper illustrates the impact of the Metrology Roadmap on the development of key measurement technology. ©2001 American Institute of Physics.

ISSN:0094-243X    

DOI:10.1063/1.1354374

出版商:AIP    

年代:1901

数据来源: AIP

摘要:

One of the most significant challenges for technology characterization and failure analysis is to keep instrumentation and techniques in step with the development of technology itself. Not only are dimensions shrinking and new materials being employed, but the rate of change is increasing. According to the 1999International Technology Roadmap for Semiconductors, “The number and difficulty of the technical challenges continue to increase as technology moves forward.”1It could be argued that technology cannot be developed without appropriate analytical techniques; nevertheless while much effort is being directed at materials and processes, only a small proportion is being directed at analysis. Whereas previous versions of the Semiconductor Industry Association roadmap contained a small number of implicit references to characterization and analysis, the 1999 ITRS contains many explicit references. It is clear that characterization is now woven through the roadmap, and technology developers in all areas appreciate the fact that new instrumentation and techniques will be required to sustain the rate of development the semiconductor industry has seen in recent years. Late in 1999, a subcommittee of the Sematech Product Analysis Forum (PAF) reviewed the ITRS and identified a “top-ten” list of challenges which the failure analysis community will face as present technologies are extended and future technologies are developed. This paper discusses the PAF top-ten list of challenges, which is based primarily on the Difficult Challenges tables from each ITRS working group. Eight of the top-ten are challenges of significant technical magnitude; only two could be considered non-technical in nature. Most of these challenges cut across several working group areas and could be considered common threads in the roadmap, ranging from fault simulation and modeling to imaging small features, from electrical defect isolation to deprocessing. While evolutionary changes can be anticipated fairly easily, revolutionary changes require large multi-faceted research efforts. Each of the ten challenges will be discussed in the context of the roadmap, and specific needs in each area will be given. ©2001 American Institute of Physics.

ISSN:0094-243X    

DOI:10.1063/1.1354375

出版商:AIP    

年代:1901

数据来源: AIP

摘要:

Many factors are coming together simultaneously, pushing current fault isolation and failure analysis methods to their limits. Greater numbers of differentiated products are emerging in shorter timeframes in a greater variety of packages, while at the same time incorporating significantly different materials, smaller geometries, and improved thermal performance at both the die and package level. This makes it more important than ever before to have test methods that quickly isolate a problem to the die or package level. A particular challenge is the analysis of fully enabled assemblies (including thermal performance options such as heat exchangers and thermal slugs; retention modules; EMI shielding; and on-board inspection). Without forecasting, the required assembly and packaging analysis tools will not be available when needed. Thus, the Sematech Assembly Analytical Forum (AAF) was formed in 1999 to focus on techniques and tools that uniquely impact packaging, to highlight the critical analytical breakthroughs necessary to identify and understand packaging/assembly defects for current and future products, and to challenge instrument vendors and universities to develop the necessary tools and techniques as an industry consortium. The techniques currently targeted by the AAF for development and/or enhancements are presented. ©2001 American Institute of Physics.

ISSN:0094-243X    

DOI:10.1063/1.1354376

出版商:AIP    

年代:1901

数据来源: AIP

摘要:

The biggest challenge facing the future of Front-End Processes at and beyond the 100 nm technology node lies in the fabrication of the basic transistor structure. That process will entail development of a higher-k gate dielectric and the associated processing of the gate stack as well as a highly-doped, ultrashallow junction contacting the advanced transistor structure. The smaller dimensions associated with continued transistor scaling, moreover, offer the opportunity for a detailed re-examination of the role and usefulness of silicon wafer specifications. Data is being developed that suggests a reduction of various contaminants and defects as well as the continued reduction of certain other wafer specifications in silicon wafers may not necessarily be required to ensure continued improvements in IC performance, although detailed yield and reliability studies are still required to fully quantify these observations. The innovative transistor structures being fabricated in three-dimensional device configurations (which may be regarded as the natural evolution of the multi-zone wafer design concept), may further de-couple the starting silicon wafer from the active transistor structure. The implications of these transistor requirements on the silicon wafer for the ensuing mesoscopic (i.e., ≈ a few 10’s nm) era may offer significant cost-of-ownership (CoO) opportunities in the relevant wafer specifications. ©2001 American Institute of Physics.

ISSN:0094-243X    

DOI:10.1063/1.1354377

出版商:AIP    

年代:1901

数据来源: AIP

摘要:

The energy band gaps of thin high-dielectric-constant (high-k) insulators such asTa2O5,Si3N4andAl2O3have been determined by measuring the energy loss spectra ofO1sorN1sphotoelectrons. From the analysis of the valence band spectra for thin high-k dielectrics prepared on metals and Si(100), the energy band profiles for metal/high-k dielectric/Si(100) systems have been determined in consideration for the measured energy bandgaps and metal work functions. Intrinsic tunneling leakage currents forTiN/Ta2O5/SiO2/Si(100)andAl/Al2O3/Si(100)systems were calculated by applying a transfer matrix method to their energy band profiles so determined. The results show that, for theTiN/Ta2O5/SiO2/Si(100)structure, the interfacialSiO2layer is a crucial factor to suppress the electron tunneling rate, while for theAl/Al2O3/Si(100)structure the tunneling current is sufficiently low even in anSiO2-equivalent thickness of 1.2 nm compared with conventionaln+-polySi/SiO2/Si(100).It is also demonstrated that total photoelectron yield spectroscopy is a useful and high-sensitive technique to evaluate the energy distribution of defect states in the high-k dielectrics and at the interfaces. ©2001 American Institute of Physics.

ISSN:0094-243X    

DOI:10.1063/1.1354378

出版商:AIP    

年代:1901

数据来源: AIP

摘要:

The microelectronics revolution has been enabled by the nearly ideal properties of silicon dioxide and its interface with silicon. Continually thinner gate oxides have been a critical feature of the overall scaling of transistor dimensions for three decades, enabling continued speed improvement even as operating voltages decrease. This era of scaling in thickness of a silicon dioxide insulator will soon come to an end, as gate tunneling current, reduced reliability, and diminishing returns in speed make further reductions impossible or unrewarding. New materials systems may provide some relief, but they have yet to show their ability to replace silicon dioxide. Truly novel approaches, such as the Vertical, Replacement Gate process, which provides more current in the same area by increasing the device perimeter, can address the same issues. ©2001 American Institute of Physics.

ISSN:0094-243X    

DOI:10.1063/1.1354379

出版商:AIP    

年代:1901

数据来源: AIP

摘要:

The performance of deep submicron devices depends heavily on the electrical properties of the gate dielectric. Electrical properties such as dielectric constant, leakage current density, interface trap and oxide trapped charge, dielectric integrity, and reliability are all critical concerns for the development of advanced gate dielectrics. This paper discusses several metrology methods based on capacitance-voltage (CV), charge-voltage (QV) and current-voltage (IV) and reviews the problems, issues and concerns associated with CV and IV metrology as IC technology has gone from 1 &mgr;m down to 0.18 &mgr;m and beyond. Issues such as proper measurement setup, equivalent circuit effects, silicon accumulation capacitance, and quantum confinement of the silicon density of states must be accounted for. In addition to these considerations, the influence of interfacial layers between the gate and the dielectric needs to be addressed. These interfacial layers can consist of organics, inorganics, and water. The paper includes the results of CV, QV and IV measurements on a number of ultra-thin oxides and advanced gate dielectrics such asTa2O5,Al2O3andZrO2.©2001 American Institute of Physics.

ISSN:0094-243X    

DOI:10.1063/1.1354380

出版商:AIP    

年代:1901

数据来源: AIP